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1.发明申请Methods and Apparatus for Providing Bit-Reversal and Multicast Functions Utilizing DMA Controller 失效使用DMA控制器提供位反转和组播功能的方法和装置公开(公告)号：US20120331185A1
公开(公告)日：2012-12-27
申请号：US13545067
申请日：2012-07-10
IPC分类号： G06F15/80
CPC分类号： G06F13/28
摘要： Techniques for providing improved data distribution to and collection from multiple memories are described. Such memories are often associated with and local to processing elements (PEs) within an array processor. Improved data transfer control within a data processing system provides support for radix 2, 4 and 8 fast Fourier transform (FFT) algorithms through data reordering or bit-reversed addressing across multiple PEs, carried out concurrently with FFT computation on a digital signal processor (DSP) array by a DMA unit. Parallel data distribution and collection through forms of multicast and packet-gather operations are also supported.
摘要翻译： 描述了用于向多个存储器提供改进的数据分配和从多个存储器收集的技术。 这种存储器通常与阵列处理器内的处理元件（PE）相关联并且位于本地。 数据处理系统中的改进的数据传输控制通过在数字信号处理器（DSP）上与FFT计算并行执行的多个PE上的数据重排序或位反转寻址来提供基数2,4和8快速傅里叶变换（FFT）算法的支持 ）数组。 还支持通过组播和数据包采集操作的并行数据分发和收集。
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2.发明申请Methods and Apparatus for Providing Bit-Reversal and Multicast Functions Utilizing DMA Controller 有权使用DMA控制器提供位反转和组播功能的方法和装置公开(公告)号：US20100257290A1
公开(公告)日：2010-10-07
申请号：US12819302
申请日：2010-06-21
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： Techniques for providing improved data distribution to and collection from multiple memories are described. Such memories are often associated with and local to processing elements (PEs) within an array processor. Improved data transfer control within a data processing system provides support for radix 2, 4 and 8 fast Fourier transform (FFT) algorithms through data reordering or bit-reversed addressing across multiple PEs, carried out concurrently with FFT computation on a digital signal processor (DSP) array by a DMA unit. Parallel data distribution and collection through forms of multicast and packet-gather operations are also supported.
摘要翻译： 描述了用于向多个存储器提供改进的数据分配和从多个存储器收集的技术。 这种存储器通常与阵列处理器内的处理元件（PE）相关联并且位于本地。 数据处理系统中的改进的数据传输控制通过在数字信号处理器（DSP）上与FFT计算并行执行的多个PE上的数据重排序或位反转寻址来提供基数2,4和8快速傅里叶变换（FFT）算法的支持 ）数组。 还支持通过组播和数据包采集操作的并行数据分发和收集。
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3.发明授权公开(公告)号：US06986020B2
公开(公告)日：2006-01-10
申请号：US10946261
申请日：2004-09-21
IPC分类号： G06F15/80
CPC分类号： G06F13/28
摘要： Techniques for providing improved data distribution to and collection from multiple memories are described. Such memories are often associated with and local to processing elements (PEs) within an array processor. Improved data transfer control within a data processing system provides support for radix 2, 4 and 8 fast Fourier transform (FFT) algorithms through data reordering or bit-reversed addressing across multiple PEs, carried out concurrently with FFT computation on a digital signal processor (DSP) array by a DMA unit. Parallel data distribution and collection through forms of multicast and packet-gather operations are also supported.
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4.发明授权Methods and apparatus for providing bit-reversal and multicast functions utilizing DMA controller 有权使用DMA控制器提供位反转和多播功能的方法和装置公开(公告)号：US06834295B2
公开(公告)日：2004-12-21
申请号：US09791940
申请日：2001-02-23
IPC分类号： G06F15167
CPC分类号： G06F13/28
摘要： Techniques for providing improved data distribution to and collection from multiple memories are described. Such memories are often associated with and local to processing elements (PEs) within an array processor. Improved data transfer control within a data processing system provides support for radix 2, 4 and 8 fast Fourier transform (FFT) algorithms through data reordering or bit-reversed addressing across multiple PEs, carried out concurrently with FFT computation on a digital signal processor (DSP) array by a DMA unit. Parallel data distribution and collection through forms of multicast and packet-gather operations are also supported.
摘要翻译： 描述了用于向多个存储器提供改进的数据分配和从多个存储器收集的技术。 这种存储器通常与阵列处理器内的处理元件（PE）相关联并且位于本地。 数据处理系统中的改进的数据传输控制通过在数字信号处理器（DSP）上与FFT计算并行执行的多个PE上的数据重排序或位反转寻址来提供基数2,4和8快速傅里叶变换（FFT）算法的支持 ）数组。 还支持通过组播和数据包采集操作的并行数据分发和收集。
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5.发明申请Methods and Apparatus for Providing Bit-Reversal and Multicast Functions Utilizing DMA Controller 审中-公开使用DMA控制器提供位反转和组播功能的方法和装置公开(公告)号：US20140075081A1
公开(公告)日：2014-03-13
申请号：US14070657
申请日：2013-11-04
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： Techniques for providing improved data distribution to and collection from multiple memories are described. Such memories are often associated with and local to processing elements (PEs) within an array processor. Improved data transfer control within a data processing system provides support for radix 2, 4 and 8 fast Fourier transform (FFT) algorithms through data reordering or bit-reversed addressing across multiple PEs, carried out concurrently with FFT computation on a digital signal processor (DSP) array by a DMA unit. Parallel data distribution and collection through forms of multicast and packet-gather operations are also supported.
摘要翻译： 描述了用于向多个存储器提供改进的数据分配和从多个存储器收集的技术。 这种存储器通常与阵列处理器内的处理元件（PE）相关联并且位于本地。 数据处理系统中的改进的数据传输控制通过在数字信号处理器（DSP）上与FFT计算并行执行的多个PE上的数据重排序或位反转寻址来提供基数2,4和8快速傅里叶变换（FFT）算法的支持 ）数组。 还支持通过组播和数据包采集操作的并行数据分发和收集。
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6.发明申请Methods and Apparatus for Providing Bit-Reversal and Multicast Functions Utilizing DMA Controller 有权使用DMA控制器提供位反转和组播功能的方法和装置公开(公告)号：US20110302333A1
公开(公告)日：2011-12-08
申请号：US13205269
申请日：2011-08-08
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： Techniques for providing improved data distribution to and collection from multiple memories are described. Such memories are often associated with and local to processing elements (PEs) within an array processor. Improved data transfer control within a data processing system provides support for radix 2, 4 and 8 fast Fourier transform (FFT) algorithms through data reordering or bit-reversed addressing across multiple PEs, carried out concurrently with FFT computation on a digital signal processor (DSP) array by a DMA unit. Parallel data distribution and collection through forms of multicast and packet-gather operations are also supported.
摘要翻译： 描述了用于向多个存储器提供改进的数据分配和从多个存储器收集的技术。 这种存储器通常与阵列处理器内的处理元件（PE）相关联并且位于本地。 数据处理系统中的改进的数据传输控制通过在数字信号处理器（DSP）上与FFT计算并行执行的多个PE上的数据重排序或位反转寻址来提供基数2,4和8快速傅里叶变换（FFT）算法的支持 ）数组。 还支持通过组播和数据包采集操作的并行数据分发和收集。
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7.发明申请公开(公告)号：US20110225392A1
公开(公告)日：2011-09-15
申请号：US13113412
申请日：2011-05-23
CPC分类号： G06F13/28
摘要： Techniques for providing improved data distribution to and collection from multiple memories are described. Such memories are often associated with and local to processing elements (PEs) within an array processor. Improved data transfer control within a data processing system provides support for radix 2, 4 and 8 fast Fourier transform (FFT) algorithms through data reordering or bit-reversed addressing across multiple PEs, carried out concurrently with FFT computation on a digital signal processor (DSP) array by a DMA unit. Parallel data distribution and collection through forms of multicast and packet-gather operations are also supported.
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公开(公告)号：US06795909B2
公开(公告)日：2004-09-21
申请号：US10114646
申请日：2002-04-01
申请人： Edwin F. Barry , Gerald G. Pechanek , Thomas L. Drabenstott , Edward A. Wolff , Nikos P. Pitsianis , Grayson Morris
发明人： Edwin F. Barry , Gerald G. Pechanek , Thomas L. Drabenstott , Edward A. Wolff , Nikos P. Pitsianis , Grayson Morris
IPC分类号： G06F1517
CPC分类号： G06F15/17381 , H04L49/1553 , H04L49/201 , H04L49/3009 , H04L49/45
摘要： Processing element to processing element switch connection control is described using a receive model that precludes communication hazards from occurring in a synchronous MIMD mode of operation. Such control allows different communication topologies and various processing effects such as an array transpose, hypercomplement or the like to be efficiently achieved utilizing architectures, such as the manifold array processing architecture. An encoded instruction method reduces the amount of state information and setup burden on the programmer taking advantage of the recognition that the majority of algorithms will use only a small fraction of all possible mux settings available. Thus, by means of transforming the PE identification based upon a communication path specified by a PE communication instruction an efficient switch control mechanism can be used. This control mechanism allows PE register broadcast operations as well as the standard mesh and hypercube communication paths over the same interconnection network. PE to PE communication instructions PEXCHG, SPRECV and SPSEND are also defined and implemented.
摘要翻译： 使用接收模型描述处理元件切换连接控制的处理元件，该接收模型排除在同步MIMD操作模式中发生通信危险。 这样的控制允许利用诸如歧管阵列处理架构的架构有效地实现不同的通信拓扑和各种处理效果，例如阵列转置，超补充等。 编码指令方法通过利用大多数算法仅使用所有可能的多路复用器设置的一小部分的识别来减少程序员的状态信息和设置负担的量。 因此，通过基于由PE通信指令指定的通信路径变换PE标识，可以使用有效的开关控制机构。 该控制机制允许PE寄存器广播操作以及相同互连网络上的标准网格和超立方体通信路径。 PE到PE通信指令PEXCHG，SPRECV和SPSEND也被定义和实现。
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公开(公告)号：US6167502A
公开(公告)日：2000-12-26
申请号：US949122
申请日：1997-10-10
CPC分类号： G06F15/8023
摘要： A manifold array topology includes processing elements, nodes, memories or the like arranged in clusters. Clusters are connected by cluster switch arrangements which advantageously allow changes of organization without physical rearrangement of processing elements. A significant reduction in the typical number of interconnections for preexisting arrays is also achieved. Fast, efficient and cost effective processing and communication result with the added benefit of ready scalability.
摘要翻译： 歧管阵列拓扑包括以簇排列的处理元件，节点，存储器等。 集群通过集群交换机布置连接，其有利地允许组织的改变而不需要处理元件的物理重排。 也实现了预先存在的阵列的典型互连数量的显着减少。 快速，高效和经济高效的处理和通信带来了可扩展性的附加优势。
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公开(公告)号：US6167501A
公开(公告)日：2000-12-26
申请号：US169256
申请日：1998-10-09
申请人： Edwin F. Barry , Gerald G. Pechanek , Thomas L. Drabenstott , Edward A. Wolff , Nikos P. Pitsianis , Grayson Morris
发明人： Edwin F. Barry , Gerald G. Pechanek , Thomas L. Drabenstott , Edward A. Wolff , Nikos P. Pitsianis , Grayson Morris
IPC分类号： G06F15/16 , G06F15/173 , G06F15/80 , H04L12/56
CPC分类号： G06F15/17381 , H04L49/1553 , H04L49/201 , H04L49/3009 , H04L49/45
摘要： Processing element to processing element switch connection control is described using a receive model that precludes communication hazards from occurring in a synchronous MIMD mode of operation. Such control allows different communication topologies and various processing effects such as an array transpose, hypercomplement or the like to be efficiently achieved utilizing architectures, such as the manifold array processing architecture. An encoded instruction method reduces the amount of state information and setup burden on the programmer taking advantage of the recognition that the majority of algorithms will use only a small fraction of all possible mux settings available. Thus, by means of transforming the PE identification based upon a communication path specified by a PE communication instruction an efficient switch control mechanism can be used. This control mechanism allows PE register broadcast operations as well as the standard mesh and hypercube communication paths over the same interconnection network. PE to PE communication instructions PEXCHG, SPRECV and SPSEND are also defined and implemented.
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