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公开(公告)号：US06795909B2
公开(公告)日：2004-09-21
申请号：US10114646
申请日：2002-04-01
申请人： Edwin F. Barry , Gerald G. Pechanek , Thomas L. Drabenstott , Edward A. Wolff , Nikos P. Pitsianis , Grayson Morris
发明人： Edwin F. Barry , Gerald G. Pechanek , Thomas L. Drabenstott , Edward A. Wolff , Nikos P. Pitsianis , Grayson Morris
IPC分类号： G06F1517
CPC分类号： G06F15/17381 , H04L49/1553 , H04L49/201 , H04L49/3009 , H04L49/45
摘要： Processing element to processing element switch connection control is described using a receive model that precludes communication hazards from occurring in a synchronous MIMD mode of operation. Such control allows different communication topologies and various processing effects such as an array transpose, hypercomplement or the like to be efficiently achieved utilizing architectures, such as the manifold array processing architecture. An encoded instruction method reduces the amount of state information and setup burden on the programmer taking advantage of the recognition that the majority of algorithms will use only a small fraction of all possible mux settings available. Thus, by means of transforming the PE identification based upon a communication path specified by a PE communication instruction an efficient switch control mechanism can be used. This control mechanism allows PE register broadcast operations as well as the standard mesh and hypercube communication paths over the same interconnection network. PE to PE communication instructions PEXCHG, SPRECV and SPSEND are also defined and implemented.
摘要翻译： 使用接收模型描述处理元件切换连接控制的处理元件，该接收模型排除在同步MIMD操作模式中发生通信危险。 这样的控制允许利用诸如歧管阵列处理架构的架构有效地实现不同的通信拓扑和各种处理效果，例如阵列转置，超补充等。 编码指令方法通过利用大多数算法仅使用所有可能的多路复用器设置的一小部分的识别来减少程序员的状态信息和设置负担的量。 因此，通过基于由PE通信指令指定的通信路径变换PE标识，可以使用有效的开关控制机构。 该控制机制允许PE寄存器广播操作以及相同互连网络上的标准网格和超立方体通信路径。 PE到PE通信指令PEXCHG，SPRECV和SPSEND也被定义和实现。
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公开(公告)号：US6167502A
公开(公告)日：2000-12-26
申请号：US949122
申请日：1997-10-10
CPC分类号： G06F15/8023
摘要： A manifold array topology includes processing elements, nodes, memories or the like arranged in clusters. Clusters are connected by cluster switch arrangements which advantageously allow changes of organization without physical rearrangement of processing elements. A significant reduction in the typical number of interconnections for preexisting arrays is also achieved. Fast, efficient and cost effective processing and communication result with the added benefit of ready scalability.
摘要翻译： 歧管阵列拓扑包括以簇排列的处理元件，节点，存储器等。 集群通过集群交换机布置连接，其有利地允许组织的改变而不需要处理元件的物理重排。 也实现了预先存在的阵列的典型互连数量的显着减少。 快速，高效和经济高效的处理和通信带来了可扩展性的附加优势。
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公开(公告)号：US6167501A
公开(公告)日：2000-12-26
申请号：US169256
申请日：1998-10-09
申请人： Edwin F. Barry , Gerald G. Pechanek , Thomas L. Drabenstott , Edward A. Wolff , Nikos P. Pitsianis , Grayson Morris
发明人： Edwin F. Barry , Gerald G. Pechanek , Thomas L. Drabenstott , Edward A. Wolff , Nikos P. Pitsianis , Grayson Morris
IPC分类号： G06F15/16 , G06F15/173 , G06F15/80 , H04L12/56
CPC分类号： G06F15/17381 , H04L49/1553 , H04L49/201 , H04L49/3009 , H04L49/45
摘要： Processing element to processing element switch connection control is described using a receive model that precludes communication hazards from occurring in a synchronous MIMD mode of operation. Such control allows different communication topologies and various processing effects such as an array transpose, hypercomplement or the like to be efficiently achieved utilizing architectures, such as the manifold array processing architecture. An encoded instruction method reduces the amount of state information and setup burden on the programmer taking advantage of the recognition that the majority of algorithms will use only a small fraction of all possible mux settings available. Thus, by means of transforming the PE identification based upon a communication path specified by a PE communication instruction an efficient switch control mechanism can be used. This control mechanism allows PE register broadcast operations as well as the standard mesh and hypercube communication paths over the same interconnection network. PE to PE communication instructions PEXCHG, SPRECV and SPSEND are also defined and implemented.
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公开(公告)号：US06769056B2
公开(公告)日：2004-07-27
申请号：US10254049
申请日：2002-09-24
IPC分类号： G06F1500
CPC分类号： G06F15/8023
摘要： A manifold array topology includes processing elements, nodes, memories or the like arranged in clusters. Clusters are connected by cluster switch arrangements which advantageously allow changes of organization without physical rearrangement of processing elements. A significant reduction in the typical number of interconnections for preexisting arrays is also achieved. Fast, efficient and cost effective processing and communication result with the added benefit of ready scalability.
摘要翻译： 歧管阵列拓扑包括以簇排列的处理元件，节点，存储器等。 集群通过集群交换机布置连接，其有利地允许组织的改变而不需要处理元件的物理重排。 也实现了预先存在的阵列的典型互连数量的显着减少。 快速，高效和经济高效的处理和通信带来了可扩展性的附加优势。
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公开(公告)号：US06470441B1
公开(公告)日：2002-10-22
申请号：US09707209
申请日：2000-11-06
IPC分类号： G06F1500
CPC分类号： G06F15/8023
摘要： A manifold array topology includes processing elements, nodes, memories or the like arranged in clusters. Clusters are connected by cluster switch arrangements which advantageously allow changes of organization without physical rearrangement of processing elements. A significant reduction in the typical number of interconnections for preexisting arrays is also achieved. Fast, efficient and cost effective processing and communication result with the added benefit of ready scalability.
摘要翻译： 歧管阵列拓扑包括以簇排列的处理元件，节点，存储器等。 集群通过集群交换机布置连接，其有利地允许组织的改变而不需要处理元件的物理重排。 也实现了预先存在的阵列的典型互连数量的显着减少。 快速，高效和经济高效的处理和通信带来了可扩展性的附加优势。
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公开(公告)号：US06366997B1
公开(公告)日：2002-04-02
申请号：US09649647
申请日：2000-08-29
申请人： Edwin F. Barry , Gerald G. Pechanek , Thomas L. Drabenstott , Edward A. Wolff , Nikos P. Pitsianis , Grayson Morris
发明人： Edwin F. Barry , Gerald G. Pechanek , Thomas L. Drabenstott , Edward A. Wolff , Nikos P. Pitsianis , Grayson Morris
IPC分类号： G06F1576
CPC分类号： G06F15/17381 , H04L49/1553 , H04L49/201 , H04L49/3009 , H04L49/45
摘要： Processing element to processing element switch connection control is described using a receive model that precludes communication hazards from occurring in a synchronous MIMD mode of operation. Such control allows different communication topologies and various processing effects such as an array transpose, hypercomplement or the like to be efficiently achieved utilizing architectures, such as the manifold array processing architecture. An encoded instruction method reduces the amount of state information and setup burden on the programmer taking advantage of the recognition that the majority of algorithms will use only a small fraction of all possible mux settings available. Thus, by means of transforming the PE identification based upon a communication path specified by a PE communication instruction an efficient switch control mechanism can be used. This control mechanism allows PE register broadcast operations as well as the standard mesh and hypercube communication paths over the same interconnection network. PE to PE communication instructions PEXCHG, SPRECV and SPSEND are also defined and implemented.
摘要翻译： 使用接收模型描述处理元件切换连接控制的处理元件，该接收模型排除在同步MIMD操作模式中发生通信危险。 这样的控制允许利用诸如歧管阵列处理架构的架构有效地实现不同的通信拓扑和各种处理效果，例如阵列转置，超补充等。 编码指令方法通过利用大多数算法仅使用所有可能的多路复用器设置的一小部分的识别来减少程序员的状态信息和设置负担的量。 因此，通过基于由PE通信指令指定的通信路径变换PE标识，可以使用有效的开关控制机构。 该控制机制允许PE寄存器广播操作以及相同互连网络上的标准网格和超立方体通信路径。 PE到PE通信指令PEXCHG，SPRECV和SPSEND也被定义和实现。
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7.发明授权Methods and apparatus to support conditional execution in a VLIW-based array processor with subword execution 有权在具有子字执行的基于VLIW的阵列处理器中支持条件执行的方法和装置公开(公告)号：US06760831B2
公开(公告)日：2004-07-06
申请号：US10114652
申请日：2002-04-01
IPC分类号： G06F1580
CPC分类号： G06F9/30094 , G06F9/30036 , G06F9/30072 , G06F9/30181 , G06F9/3842 , G06F9/3885 , G06F9/3887 , G06F9/3891 , G06F15/8007
摘要： General purpose flags (ACFs) are defined and encoded utilizing a hierarchical one-, two- or three-bit encoding. Each added bit provides a superset of the previous functionality. With condition combination, a sequential series of conditional branches based on complex conditions may be avoided and complex conditions can then be used for conditional execution. ACF generation and use can be specified by the programmer. By varying the number of flags affected, conditional operation parallelism can be widely varied, for example, from mono-processing to octal-processing in VLIW execution, and across an array of processing elements (PE)s. Multiple PEs can generate condition information at the same time with the programmer being able to specify a conditional execution in one processor based upon a condition generated in a different processor using the communications interface between the processing elements to transfer the conditions. Each processor in a multiple processor array may independently have different units conditionally operate based upon their ACFs.
摘要翻译： 使用分层一位，二位或三位编码来定义和编码通用标志（ACF）。 每个添加的位提供了先前功能的超集。 通过条件组合，可以避免基于复杂条件的顺序一系列条件分支，然后可以将复杂条件用于条件执行。 ACF生成和使用可以由程序员指定。 通过改变受影响的标志的数量，条件操作并行性可以被广泛地变化，例如，从VLIW执行中的单处理到八进制处理，以及处理元件（PE）的阵列。 多个PE可以同时生成条件信息，程序员能够基于使用处理元件之间的通信接口在不同的处理器中生成的条件来指定一个处理器中的条件执行以传送条件。 多处理器阵列中的每个处理器可以独立地具有基于它们的ACF有条件地操作的不同单元。
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8.发明授权Methods and apparatus to support conditional execution in a VLIW-based array processor with subword execution 失效在具有子字执行的基于VLIW的阵列处理器中支持条件执行的方法和装置公开(公告)号：US06954842B2
公开(公告)日：2005-10-11
申请号：US10650301
申请日：2003-08-28
CPC分类号： G06F9/30094 , G06F9/30036 , G06F9/30072 , G06F9/30181 , G06F9/3842 , G06F9/3885 , G06F9/3887 , G06F9/3891 , G06F15/8007
摘要： General purpose flags (ACFs) are defined and encoded utilizing a hierarchical one-, two- or three-bit encoding. Each added bit provides a superset of the previous functionality. With condition combination, a sequential series of conditional branches based on complex conditions may be avoided and complex conditions can then be used for conditional execution. ACF generation and use can be specified by the programmer. By varying the number of flags affected, conditional operation parallelism can be widely varied, for example, from mono-processing to octal-processing in VLIW execution, and across an array of processing elements (PE)s. Multiple PEs can generate condition information at the same time with the programmer being able to specify a conditional execution in one processor based upon a condition generated in a different processor using the communications interface between the processing elements to transfer the conditions. Each processor in a multiple processor array may independently have different units conditionally operate based upon their ACFs.
摘要翻译： 使用分层一位，二位或三位编码来定义和编码通用标志（ACF）。 每个添加的位提供了先前功能的超集。 通过条件组合，可以避免基于复杂条件的顺序一系列条件分支，然后可以将复杂条件用于条件执行。 ACF生成和使用可以由程序员指定。 通过改变受影响的标志的数量，条件操作并行性可以被广泛地变化，例如，从VLIW执行中的单处理到八进制处理，以及处理元件（PE）的阵列。 多个PE可以同时生成条件信息，程序员能够基于使用处理元件之间的通信接口在不同的处理器中生成的条件来指定一个处理器中的条件执行以传送条件。 多处理器阵列中的每个处理器可以独立地具有基于它们的ACF有条件地操作的不同单元。
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9.发明授权Methods and apparatus to support conditional execution in a VLIW-based array processor with subword execution 有权在具有子字执行的基于VLIW的阵列处理器中支持条件执行的方法和装置公开(公告)号：US06366999B1
公开(公告)日：2002-04-02
申请号：US09238446
申请日：1999-01-28
IPC分类号： G06F1580
CPC分类号： G06F9/30094 , G06F9/30036 , G06F9/30072 , G06F9/30181 , G06F9/3842 , G06F9/3885 , G06F9/3887 , G06F9/3891 , G06F15/8007
摘要： General purpose flags (ACFs) are defined and encoded utilizing a hierarchical one-, two- or three-bit encoding. Each added bit provides a superset of the previous functionality. With condition combination, a sequential series of conditional branches based on complex conditions may be avoided and complex conditions can then be used for conditional execution. ACF generation and use can be specified by the programmer. By varying the number of flags affected, conditional operation parallelism can be widely varied, for example, from mono-processing to octal-processing in VLIW execution, and across an array of processing elements (PE)s. Multiple PEs can generate condition information at the same time with the programmer being able to specify a conditional execution in one processor based upon a condition generated in a different processor using the communications interface between the processing elements to transfer the conditions. Each processor in a multiple processor array may independently have different units conditionally operate based upon their ACFs.
摘要翻译： 使用分层一位，二位或三位编码来定义和编码通用标志（ACF）。 每个添加的位提供了先前功能的超集。 通过条件组合，可以避免基于复杂条件的顺序一系列条件分支，然后可以将复杂条件用于条件执行。 ACF生成和使用可以由程序员指定。 通过改变受影响的标志的数量，条件操作并行性可以被广泛地变化，例如，从VLIW执行中的单处理到八进制处理，以及处理元件（PE）的阵列。 多个PE可以同时生成条件信息，程序员能够基于使用处理元件之间的通信接口在不同的处理器中生成的条件来指定一个处理器中的条件执行以传送条件。 多处理器阵列中的每个处理器可以独立地具有基于它们的ACF有条件地操作的不同单元。
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10.发明授权Constructing database representing manifold array architecture instruction set for use in support tool code creation 有权构建表示用于支持工具代码创建的多支数组架构指令集的数据库公开(公告)号：US06748517B1
公开(公告)日：2004-06-08
申请号：US09599980
申请日：2000-06-22
申请人： Gerald G. Pechanek , David Carl Strube , Edwin Frank Barry , Charles W. Kurak, Jr. , Carl Donald Busboom , Dale Edward Schneider , Nikos P. Pitsianis , Grayson Morris , Edward A. Wolff , Patrick R. Marchand , Ricardo E. Rodriguez , Marco C. Jacobs
发明人： Gerald G. Pechanek , David Carl Strube , Edwin Frank Barry , Charles W. Kurak, Jr. , Carl Donald Busboom , Dale Edward Schneider , Nikos P. Pitsianis , Grayson Morris , Edward A. Wolff , Patrick R. Marchand , Ricardo E. Rodriguez , Marco C. Jacobs
IPC分类号： G06F944
CPC分类号： G06F15/82 , G06F9/30145 , G06F11/263 , Y10S707/99943
摘要： Details of a highly cost effective and efficient implementation of a manifold array (ManArray) architecture and instruction syntax for use therewith are described herein. Various aspects of this approach include the regularity of the syntax, the relative ease with which the instruction set can be represented in database form, the ready ability with which tools can be created, the ready generation of self-checking codes and parameterized testcases. Parameterizations can be fairly easily mapped and system maintenance is significantly simplified.
摘要翻译： 这里描述了使用歧管阵列（ManArray）架构和指令语法的高成本有效和高效的实现的细节。 该方法的各个方面包括语法的规律性，可以以数据库形式表示指令集的相对容易程度，可以创建工具的准备就绪能力，自检代码的准备生成和参数化测试用例。 可以很容易地映射参数化，并显着简化系统维护。
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