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公开(公告)号：US20110320866A1
公开(公告)日：2011-12-29
申请号：US12822437
申请日：2010-06-24
IPC分类号： G06F11/14
CPC分类号： G06F11/1048
摘要： Dynamic pipeline cache error correction includes receiving a request to perform an operation that requires a storage cache slot, the storage cache slot residing in a cache. The dynamic pipeline cache error correction also includes accessing the storage cache slot, determining a cache hit for the storage cache slot, identifying and correcting any correctable soft errors associated with the storage cache slot. The dynamic cache error correction further includes updating the cache with results of corrected data.
摘要翻译： 动态流水线高速缓存错误校正包括接收执行需要存储高速缓存时隙的操作的请求，存储高速缓冲存储器时隙驻留在高速缓存中。 动态流水线高速缓存错误校正还包括访问存储高速缓存时隙，确定存储高速缓存时隙的高速缓存命中，识别和校正与存储高速缓存槽相关联的任何可校正的软错误。 动态高速缓存错误校正还包括用校正数据的结果更新高速缓存。
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公开(公告)号：US08392621B2
公开(公告)日：2013-03-05
申请号：US12820589
申请日：2010-06-22
申请人： Ekaterina M. Ambroladze , Deanna Postles Dunn Berger , Michael Fee , Arthur J. O'Neill, Jr. , Diana Lynn Orf , Robert J. Sonnelitter, III
发明人： Ekaterina M. Ambroladze , Deanna Postles Dunn Berger , Michael Fee , Arthur J. O'Neill, Jr. , Diana Lynn Orf , Robert J. Sonnelitter, III
IPC分类号： G06F3/00
CPC分类号： G06F11/0751 , G06F11/0724 , G06F11/073 , G06F12/0897 , Y02D10/13
摘要： A method of managing a temporary memory includes: receiving a request to transfer data from a source location to a destination location, the data transfer request associated with an operation to be performed, the operation selected from an input into an intermediate temporary memory and an output; checking a two-state indicator associated with the temporary memory, the two-state indicator having a first state indicating that an immediately preceding operation on the temporary memory was an input to the temporary memory and a second state indicating that the immediately preceding operation was an output from the temporary memory; and performing the operation responsive to one of: the operation being an input operation and the two-state indicator being in the second state, indicating that the immediately preceding operation was an output; and the operation being an output operation and the two-state indicator being in the first state, indicating that the immediately preceding operation was an input.
摘要翻译： 管理临时存储器的方法包括：接收从源位置传送数据到目的地位置的请求，与要执行的操作相关联的数据传输请求，从输入中选择的中间临时存储器和输出 ; 检查与临时存储器相关联的两状态指示符，两状态指示符具有指示临时存储器上的紧接在前的操作是临时存储器的输入的第一状态，以及指示紧接在前的操作是第二状态的第二状态 从临时存储器输出; 并且响应于以下操作中的一个执行操作：作为输入操作的操作和处于第二状态的两状态指示器，指示紧接在前的操作是输出; 操作是输出操作，两状态指示灯处于第一状态，表示紧接在前的操作是输入。
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公开(公告)号：US08671267B2
公开(公告)日：2014-03-11
申请号：US12822359
申请日：2010-06-24
申请人： Ekaterina M. Ambroladze , Deanna Postles Dunn Berger , Michael Fee , Christine C. Jones , Arthur J. O'Neill, Jr. , Diana Lynn Orf , Robert J. Sonnelitter, III
发明人： Ekaterina M. Ambroladze , Deanna Postles Dunn Berger , Michael Fee , Christine C. Jones , Arthur J. O'Neill, Jr. , Diana Lynn Orf , Robert J. Sonnelitter, III
CPC分类号： G06F9/3867 , G06F11/3419 , G06F11/3466 , G06F2201/88
摘要： A pipelined processing device includes: a device controller configured to receive a request to perform an operation; a plurality of subcontrollers configured to receive at least one instruction associated with the operation, each of the plurality of subcontrollers including a counter configured to generate an active time value indicating at least a portion of a time taken to process the at least one instruction; a pipeline processor configured to receive and process the at least one instruction, the pipeline processor configured to receive the active time value; and a shared pipeline storage area configured to store the active time value for each of the plurality of subcontrollers.
摘要翻译： 流水线处理装置包括：设备控制器，被配置为接收执行操作的请求; 多个子控制器被配置为接收与所述操作相关联的至少一个指令，所述多个子控制器中的每一个包括配置成生成指示处理所述至少一个指令所花费的时间的至少一部分的活动时间值的计数器; 流水线处理器，被配置为接收和处理所述至少一个指令，所述流水线处理器被配置为接收所述活动时间值; 以及共享流水线存储区域，被配置为存储多个子控制器中的每一个的活动时间值。
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公开(公告)号：US08522076B2
公开(公告)日：2013-08-27
申请号：US12821871
申请日：2010-06-23
申请人： Ekaterina M. Ambroladze , Deanna Postles Dunn Berger , Michael Fee , Arthur J. O'Neill, Jr. , Diana Lynn Orf , Robert J. Sonnelitter, III
发明人： Ekaterina M. Ambroladze , Deanna Postles Dunn Berger , Michael Fee , Arthur J. O'Neill, Jr. , Diana Lynn Orf , Robert J. Sonnelitter, III
IPC分类号： G06F11/00
CPC分类号： G06F11/0751 , G06F11/0724 , G06F11/0793
摘要： A pipelined processing device includes: a processor configured to receive a request to perform an operation; a plurality of processing controllers configured to receive at least one instruction associated with the operation, each of the plurality of processing controllers including a memory to store at least one instruction therein; a pipeline processor configured to receive and process the at least one instruction, the pipeline processor including shared error detection logic configured to detect a parity error in the at least one instruction as the at least one instruction is processed in a pipeline and generate an error signal; and a pipeline bus connected to each of the plurality of processing controllers and configured to communicate the error signal from the error detection logic.
摘要翻译： 流水线处理装置包括：被配置为接收执行操作的请求的处理器; 多个处理控制器，被配置为接收与所述操作相关联的至少一个指令，所述多个处理控制器中的每个处理控制器包括用于在其中存储至少一个指令的存储器; 流水线处理器，被配置为接收和处理所述至少一个指令，所述流水线处理器包括被配置为在流水线中处理所述至少一个指令时检测所述至少一个指令中的奇偶校验错误的共享错误检测逻辑，并且生成错误信号 ; 以及连接到所述多个处理控制器中的每个处理控制器并被配置为传送来自所述错误检测逻辑的所述错误信号的流水线总线。
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公开(公告)号：US20110320779A1
公开(公告)日：2011-12-29
申请号：US12822359
申请日：2010-06-24
申请人： Ekaterina M. Ambroladze , Deanna Postles Dunn Berger , Michael Fee , Christine C. Jones , Arthur J. O'Neill, JR. , Diana L. Orf , Robert J. Sonnelitter, III
发明人： Ekaterina M. Ambroladze , Deanna Postles Dunn Berger , Michael Fee , Christine C. Jones , Arthur J. O'Neill, JR. , Diana L. Orf , Robert J. Sonnelitter, III
IPC分类号： G06F9/30
CPC分类号： G06F9/3867 , G06F11/3419 , G06F11/3466 , G06F2201/88
摘要： A pipelined processing device includes: a device controller configured to receive a request to perform an operation; a plurality of subcontrollers configured to receive at least one instruction associated with the operation, each of the plurality of subcontrollers including a counter configured to generate an active time value indicating at least a portion of a time taken to process the at least one instruction; a pipeline processor configured to receive and process the at least one instruction, the pipeline processor configured to receive the active time value; and a shared pipeline storage area configured to store the active time value for each of the plurality of subcontrollers.
摘要翻译： 流水线处理装置包括：设备控制器，被配置为接收执行操作的请求; 多个子控制器被配置为接收与所述操作相关联的至少一个指令，所述多个子控制器中的每一个包括配置成生成指示处理所述至少一个指令所花费的时间的至少一部分的活动时间值的计数器; 流水线处理器，被配置为接收和处理所述至少一个指令，所述流水线处理器被配置为接收所述活动时间值; 以及共享流水线存储区域，被配置为存储多个子控制器中的每一个的活动时间值。
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公开(公告)号：US08327070B2
公开(公告)日：2012-12-04
申请号：US12822486
申请日：2010-06-24
IPC分类号： G06F12/00
CPC分类号： G06F12/1408 , G06F12/0802
摘要： A computer implemented method of optimizing sequential data fetches in a computer system is provided. The method includes fetching a data segment from a main memory, the data segment having a plurality of target data entries; extracting a first portion of the data segment and storing the first portion into a target data cache, the first portion having a first target data entry; and storing the data segment into an intermediate cache line buffer in communication with the target data cache to enable subsequent fetches to a number of target data entries in the data segment.
摘要翻译： 提供了一种在计算机系统中优化顺序数据提取的计算机实现的方法。 该方法包括从主存储器获取数据段，该数据段具有多个目标数据条目; 提取所述数据段的第一部分并将所述第一部分存储到目标数据高速缓存中，所述第一部分具有第一目标数据条目; 以及将数据段存储到与目标数据高速缓存进行通信的中间高速缓存行缓冲器中，以便能够随后提取数据段中的多个目标数据条目。
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公开(公告)号：US20110320740A1
公开(公告)日：2011-12-29
申请号：US12822486
申请日：2010-06-24
IPC分类号： G06F12/08
CPC分类号： G06F12/1408 , G06F12/0802
摘要： A computer implemented method of optimizing sequential data fetches in a computer system is provided. The method includes fetching a data segment from a main memory, the data segment having a plurality of target data entries; extracting a first portion of the data segment and storing the first portion into a target data cache, the first portion having a first target data entry; and storing the data segment into an intermediate cache line buffer in communication with the target data cache to enable subsequent fetches to a number target data entries in the data segment.
摘要翻译： 提供了一种在计算机系统中优化顺序数据提取的计算机实现的方法。 该方法包括从主存储器获取数据段，该数据段具有多个目标数据条目; 提取所述数据段的第一部分并将所述第一部分存储到目标数据高速缓存中，所述第一部分具有第一目标数据条目; 以及将数据段存储到与目标数据高速缓存通信的中间高速缓存行缓冲器中，以便能够随后提取数据段中的数目目标数据条目。
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公开(公告)号：US08645796B2
公开(公告)日：2014-02-04
申请号：US12822437
申请日：2010-06-24
IPC分类号： G11C29/00
CPC分类号： G06F11/1048
摘要： Dynamic pipeline cache error correction includes receiving a request to perform an operation that requires a storage cache slot, the storage cache slot residing in a cache. The dynamic pipeline cache error correction also includes accessing the storage cache slot, determining a cache hit for the storage cache slot, identifying and correcting any correctable soft errors associated with the storage cache slot. The dynamic cache error correction further includes updating the cache with results of corrected data.
摘要翻译： 动态流水线高速缓存错误校正包括接收执行需要存储高速缓存时隙的操作的请求，存储高速缓冲存储器时隙驻留在高速缓存中。 动态流水线高速缓存错误校正还包括访问存储高速缓存时隙，确定存储高速缓存时隙的高速缓存命中，识别和校正与存储高速缓存槽相关联的任何可校正的软错误。 动态高速缓存错误校正还包括用校正数据的结果更新高速缓存。
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公开(公告)号：US20110320855A1
公开(公告)日：2011-12-29
申请号：US12821871
申请日：2010-06-23
申请人： Ekaterina M. Ambroladze , Deanna Postles Dunn Berger , Michael Fee , Arthur J. O'Neill, JR. , Diana Lynn Orf , Robert J. Sonnelitter, III
发明人： Ekaterina M. Ambroladze , Deanna Postles Dunn Berger , Michael Fee , Arthur J. O'Neill, JR. , Diana Lynn Orf , Robert J. Sonnelitter, III
IPC分类号： G06F11/07
CPC分类号： G06F11/0751 , G06F11/0724 , G06F11/0793
摘要： A pipelined processing device includes: a processor configured to receive a request to perform an operation; a plurality of processing controllers configured to receive at least one instruction associated with the operation, each of the plurality of processing controllers including a memory to store at least one instruction therein; a pipeline processor configured to receive and process the at least one instruction, the pipeline processor including shared error detection logic configured to detect a parity error in the at least one instruction as the at least one instruction is processed in a pipeline and generate an error signal; and a pipeline bus connected to each of the plurality of processing controllers and configured to communicate the error signal from the error detection logic.
摘要翻译： 流水线处理装置包括：被配置为接收执行操作的请求的处理器; 多个处理控制器，被配置为接收与所述操作相关联的至少一个指令，所述多个处理控制器中的每个处理控制器包括用于在其中存储至少一个指令的存储器; 流水线处理器，被配置为接收和处理所述至少一个指令，所述流水线处理器包括被配置为在流水线中处理所述至少一个指令时检测所述至少一个指令中的奇偶校验错误的共享错误检测逻辑，并且生成错误信号 ; 以及连接到所述多个处理控制器中的每个处理控制器并被配置为传送来自所述错误检测逻辑的所述错误信号的流水线总线。
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公开(公告)号：US20110314183A1
公开(公告)日：2011-12-22
申请号：US12820589
申请日：2010-06-22
申请人： Ekaterina M. Ambroladze , Deanna Postles Dunn Berger , Michael Fee , Arthur J. O'Neill, JR. , Diana Lynn Orf , Robert J. Sonnelitter, III
发明人： Ekaterina M. Ambroladze , Deanna Postles Dunn Berger , Michael Fee , Arthur J. O'Neill, JR. , Diana Lynn Orf , Robert J. Sonnelitter, III
CPC分类号： G06F11/0751 , G06F11/0724 , G06F11/073 , G06F12/0897 , Y02D10/13
摘要： A method of managing a temporary memory includes: receiving a request to transfer data from a source location to a destination location, the data transfer request associated with an operation to be performed, the operation selected from an input into an intermediate temporary memory and an output; checking a two-state indicator associated with the temporary memory, the two-state indicator having a first state indicating that an immediately preceding operation on the temporary memory was an input to the temporary memory and a second state indicating that the immediately preceding operation was an output from the temporary memory; and performing the operation responsive to one of: the operation being an input operation and the two-state indicator being in the second state, indicating that the immediately preceding operation was an output; and the operation being an output operation and the two-state indicator being in the first state, indicating that the immediately preceding operation was an input.
摘要翻译： 管理临时存储器的方法包括：接收从源位置传送数据到目的地位置的请求，与要执行的操作相关联的数据传输请求，从输入中选择的中间临时存储器和输出 ; 检查与临时存储器相关联的两状态指示符，两状态指示符具有指示临时存储器上的紧接在前的操作是临时存储器的输入的第一状态，以及指示紧接在前的操作是第二状态的第二状态 从临时存储器输出; 并且响应于以下操作中的一个执行操作：作为输入操作的操作和处于第二状态的两状态指示器，指示紧接在前的操作是输出; 操作是输出操作，两状态指示灯处于第一状态，表示紧接在前的操作是输入。
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