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    ERROR DETECTION AND RECOVERY IN A SHARED PIPELINE
    2.
    发明申请
    ERROR DETECTION AND RECOVERY IN A SHARED PIPELINE 失效
    在共享管道中的错误检测和恢复

    公开(公告)号：US20110320855A1

    公开(公告)日：2011-12-29

    申请号：US12821871

    申请日：2010-06-23

    申请人： Ekaterina M. Ambroladze ,  Deanna Postles Dunn Berger ,  Michael Fee ,  Arthur J. O'Neill, JR. ,  Diana Lynn Orf ,  Robert J. Sonnelitter, III

    发明人： Ekaterina M. Ambroladze ,  Deanna Postles Dunn Berger ,  Michael Fee ,  Arthur J. O'Neill, JR. ,  Diana Lynn Orf ,  Robert J. Sonnelitter, III

    IPC分类号： G06F11/07

    CPC分类号： G06F11/0751 ,  G06F11/0724 ,  G06F11/0793

    摘要： A pipelined processing device includes: a processor configured to receive a request to perform an operation; a plurality of processing controllers configured to receive at least one instruction associated with the operation, each of the plurality of processing controllers including a memory to store at least one instruction therein; a pipeline processor configured to receive and process the at least one instruction, the pipeline processor including shared error detection logic configured to detect a parity error in the at least one instruction as the at least one instruction is processed in a pipeline and generate an error signal; and a pipeline bus connected to each of the plurality of processing controllers and configured to communicate the error signal from the error detection logic.

    摘要翻译： 流水线处理装置包括：被配置为接收执行操作的请求的处理器; 多个处理控制器，被配置为接收与所述操作相关联的至少一个指令，所述多个处理控制器中的每个处理控制器包括用于在其中存储至少一个指令的存储器; 流水线处理器，被配置为接收和处理所述至少一个指令，所述流水线处理器包括被配置为在流水线中处理所述至少一个指令时检测所述至少一个指令中的奇偶校验错误的共享错误检测逻辑，并且生成错误信号 ; 以及连接到所述多个处理控制器中的每个处理控制器并被配置为传送来自所述错误检测逻辑的所述错误信号的流水线总线。

    SYSTEM AND METHOD FOR MANAGING DATAFLOW IN A TEMPORARY MEMORY
    3.
    发明申请
    SYSTEM AND METHOD FOR MANAGING DATAFLOW IN A TEMPORARY MEMORY 失效
    用于管理临时存储器中的数据流的系统和方法

    公开(公告)号：US20110314183A1

    公开(公告)日：2011-12-22

    申请号：US12820589

    申请日：2010-06-22

    申请人： Ekaterina M. Ambroladze ,  Deanna Postles Dunn Berger ,  Michael Fee ,  Arthur J. O'Neill, JR. ,  Diana Lynn Orf ,  Robert J. Sonnelitter, III

    发明人： Ekaterina M. Ambroladze ,  Deanna Postles Dunn Berger ,  Michael Fee ,  Arthur J. O'Neill, JR. ,  Diana Lynn Orf ,  Robert J. Sonnelitter, III

    IPC分类号： G06F3/00 ,  G06F5/14

    CPC分类号： G06F11/0751 ,  G06F11/0724 ,  G06F11/073 ,  G06F12/0897 ,  Y02D10/13

    摘要： A method of managing a temporary memory includes: receiving a request to transfer data from a source location to a destination location, the data transfer request associated with an operation to be performed, the operation selected from an input into an intermediate temporary memory and an output; checking a two-state indicator associated with the temporary memory, the two-state indicator having a first state indicating that an immediately preceding operation on the temporary memory was an input to the temporary memory and a second state indicating that the immediately preceding operation was an output from the temporary memory; and performing the operation responsive to one of: the operation being an input operation and the two-state indicator being in the second state, indicating that the immediately preceding operation was an output; and the operation being an output operation and the two-state indicator being in the first state, indicating that the immediately preceding operation was an input.

    摘要翻译： 管理临时存储器的方法包括：接收从源位置传送数据到目的地位置的请求，与要执行的操作相关联的数据传输请求，从输入中选择的中间临时存储器和输出 ; 检查与临时存储器相关联的两状态指示符，两状态指示符具有指示临时存储器上的紧接在前的操作是临时存储器的输入的第一状态，以及指示紧接在前的操作是第二状态的第二状态 从临时存储器输出; 并且响应于以下操作中的一个执行操作：作为输入操作的操作和处于第二状态的两状态指示器，指示紧接在前的操作是输出; 操作是输出操作，两状态指示灯处于第一状态，表示紧接在前的操作是输入。

    Error detection and recovery in a shared pipeline
    5.
    发明授权
    Error detection and recovery in a shared pipeline 失效
    共享管道中的错误检测和恢复

    公开(公告)号：US08522076B2

    公开(公告)日：2013-08-27

    申请号：US12821871

    申请日：2010-06-23

    申请人： Ekaterina M. Ambroladze ,  Deanna Postles Dunn Berger ,  Michael Fee ,  Arthur J. O'Neill, Jr. ,  Diana Lynn Orf ,  Robert J. Sonnelitter, III

    发明人： Ekaterina M. Ambroladze ,  Deanna Postles Dunn Berger ,  Michael Fee ,  Arthur J. O'Neill, Jr. ,  Diana Lynn Orf ,  Robert J. Sonnelitter, III

    IPC分类号： G06F11/00

    CPC分类号： G06F11/0751 ,  G06F11/0724 ,  G06F11/0793

    摘要： A pipelined processing device includes: a processor configured to receive a request to perform an operation; a plurality of processing controllers configured to receive at least one instruction associated with the operation, each of the plurality of processing controllers including a memory to store at least one instruction therein; a pipeline processor configured to receive and process the at least one instruction, the pipeline processor including shared error detection logic configured to detect a parity error in the at least one instruction as the at least one instruction is processed in a pipeline and generate an error signal; and a pipeline bus connected to each of the plurality of processing controllers and configured to communicate the error signal from the error detection logic.

    摘要翻译： 流水线处理装置包括：被配置为接收执行操作的请求的处理器; 多个处理控制器，被配置为接收与所述操作相关联的至少一个指令，所述多个处理控制器中的每个处理控制器包括用于在其中存储至少一个指令的存储器; 流水线处理器，被配置为接收和处理所述至少一个指令，所述流水线处理器包括被配置为在流水线中处理所述至少一个指令时检测所述至少一个指令中的奇偶校验错误的共享错误检测逻辑，并且生成错误信号 ; 以及连接到所述多个处理控制器中的每个处理控制器并被配置为传送来自所述错误检测逻辑的所述错误信号的流水线总线。

    Managing dataflow in a temporary memory
    6.
    发明授权
    Managing dataflow in a temporary memory 失效
    在临时内存中管理数据流

    公开(公告)号：US08392621B2

    公开(公告)日：2013-03-05

    申请号：US12820589

    申请日：2010-06-22

    申请人： Ekaterina M. Ambroladze ,  Deanna Postles Dunn Berger ,  Michael Fee ,  Arthur J. O'Neill, Jr. ,  Diana Lynn Orf ,  Robert J. Sonnelitter, III

    发明人： Ekaterina M. Ambroladze ,  Deanna Postles Dunn Berger ,  Michael Fee ,  Arthur J. O'Neill, Jr. ,  Diana Lynn Orf ,  Robert J. Sonnelitter, III

    IPC分类号： G06F3/00

    CPC分类号： G06F11/0751 ,  G06F11/0724 ,  G06F11/073 ,  G06F12/0897 ,  Y02D10/13

    摘要： A method of managing a temporary memory includes: receiving a request to transfer data from a source location to a destination location, the data transfer request associated with an operation to be performed, the operation selected from an input into an intermediate temporary memory and an output; checking a two-state indicator associated with the temporary memory, the two-state indicator having a first state indicating that an immediately preceding operation on the temporary memory was an input to the temporary memory and a second state indicating that the immediately preceding operation was an output from the temporary memory; and performing the operation responsive to one of: the operation being an input operation and the two-state indicator being in the second state, indicating that the immediately preceding operation was an output; and the operation being an output operation and the two-state indicator being in the first state, indicating that the immediately preceding operation was an input.

    摘要翻译： 管理临时存储器的方法包括：接收从源位置传送数据到目的地位置的请求，与要执行的操作相关联的数据传输请求，从输入中选择的中间临时存储器和输出 ; 检查与临时存储器相关联的两状态指示符，两状态指示符具有指示临时存储器上的紧接在前的操作是临时存储器的输入的第一状态，以及指示紧接在前的操作是第二状态的第二状态 从临时存储器输出; 并且响应于以下操作中的一个执行操作：作为输入操作的操作和处于第二状态的两状态指示器，指示紧接在前的操作是输出; 操作是输出操作，两状态指示灯处于第一状态，表示紧接在前的操作是输入。

    Dynamic multi-level cache including resource access fairness scheme
    10.
    发明授权
    Dynamic multi-level cache including resource access fairness scheme 失效
    动态多级缓存包括资源访问公平性方案

    公开(公告)号：US08447905B2

    公开(公告)日：2013-05-21

    申请号：US12821739

    申请日：2010-06-23

    申请人： Ekaterina M. Ambroladze ,  Deanna Postles Dunn Berger ,  Diana Lynn Orf ,  Robert J. Sonnelitter, III

    发明人： Ekaterina M. Ambroladze ,  Deanna Postles Dunn Berger ,  Diana Lynn Orf ,  Robert J. Sonnelitter, III

    IPC分类号： G06F13/18

    CPC分类号： G06F13/1642 ,  G06F12/0811 ,  G06F12/084

    摘要： An apparatus for controlling access to a resource includes a shared pipeline configured to communicate with the resource, a plurality of command queues configured to form instructions for the shared pipeline and an arbiter coupled between the shared pipeline and the plurality of command queues configured to grant access to the shared pipeline to a one of the plurality of command queues based on a first priority scheme in a first operating mode. The apparatus also includes interface logic coupled to the arbiter and configured to determine that contention for access to the resource exists among the plurality of command queues and to cause the arbiter to grant access to the shared pipeline based on a second priority scheme in second operating mode.

    摘要翻译： 用于控制对资源的访问的装置包括被配置为与资源通信的共享流水线，多个命令队列，被配置为形成用于共享流水线的指令，以及耦合在共享流水线与被配置为授权访问的多个命令队列之间的仲裁器 基于第一操作模式中的第一优先级方案将所述共享流水线传送到所述多个命令队列中的一个。 该装置还包括耦合到仲裁器并被配置为确定在多个命令队列中存在对资源的访问的竞争的接口逻辑，并且使得仲裁器基于第二操作模式中的第二优先级方案来允许对共享流水线的访问 。