公开(公告)号：US20250120159A1

公开(公告)日：2025-04-10

申请号：US18887701

申请日：2024-09-17

Applicant: Electronics and Telecommunications Research Institute

Inventor： Sung Haeng CHO ,  Chihun SUNG ,  Sooji NAM

IPC: H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: Provided is a thin film transistor including a substrate, a channel layer on the substrate, a first source/drain electrode and a second source/drain electrode spaced apart on the substrate and on the channel layer in a first direction parallel to the substrate, a gate insulation layer on the substrate, the channel layer, the first source/drain electrode, and the second source/drain electrode, and a gate electrode on the gate insulation layer between the first and second source/drain electrodes, wherein the uppermost level of the gate electrode is substantially the same as the uppermost level of the gate insulation layer.

公开(公告)号：US20250118357A1

公开(公告)日：2025-04-10

申请号：US18892187

申请日：2024-09-20

Applicant: Electronics and Telecommunications Research Institute

Inventor： Sooji NAM ,  Sung Haeng CHO ,  Jeho NA ,  Chihun SUNG ,  Kyunghee CHOI ,  Jung Hoon HAN

IPC: G11C11/4096 ,  H10B12/00

Abstract: Provided is a semiconductor device including a substrate, a first transistor on the substrate, an interlayer insulating layer covering the first transistor, a second transistor on the interlayer insulating layer, and a storage node contact passing through the interlayer insulating layer, and connecting any one of source/drain electrodes of the first transistor and a gate electrode of the second transistor, wherein a first channel pattern of the first transistor may include an n-type oxide transistor, and a second channel pattern of the second transistor may include an p-type oxide transistor.