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    TRANSISTOR AND METHOD OF FABRICATING THE SAME
    2.
    发明申请
    TRANSISTOR AND METHOD OF FABRICATING THE SAME 有权
    晶体管及其制造方法

    公开(公告)号：US20140367689A1

    公开(公告)日：2014-12-18

    申请号：US14192239

    申请日：2014-02-27

    Applicant: Electronics and Telecommunications Research Institute

    Inventor： Sung Haeng CHO ,  Sang-Hee PARK ,  Chi-Sun HWANG

    IPC: H01L29/786 ,  H01L29/66

    CPC classification number: H01L29/41775 ,  H01L29/0847 ,  H01L29/41733 ,  H01L29/41758 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/786 ,  H01L29/78603 ,  H01L29/7869

    Abstract: Provided is a transistor. The transistor includes: a substrate; a semiconductor layer provided on the substrate and having one side vertical to the substrate and the other side facing the one side; a first electrode extending along the substrate and contacting the one side of the semiconductor layer; a second electrode extending along the substrate and contacting the other side of the semiconductor layer; a conductive wire disposed on the first electrode and spaced from the second electrode; a gate electrode provided on the semiconductor layer; and a gate insulating layer disposed between the semiconductor layer and the gate electrode, wherein the semiconductor layer, the first electrode, and the second electrode have a coplanar.

    Abstract translation: 提供一种晶体管。 晶体管包括：衬底; 半导体层，其设置在所述基板上，并且具有与所述基板垂直的一侧，所述另一侧面向所述一侧; 沿所述基板延伸并接触所述半导体层的一侧的第一电极; 第二电极，沿着衬底延伸并接触半导体层的另一侧; 布置在所述第一电极上并与所述第二电极间隔开的导线; 设置在所述半导体层上的栅电极; 以及设置在所述半导体层和所述栅电极之间的栅绝缘层，其中所述半导体层，所述第一电极和所述第二电极具有共面。

    TRANSISTOR AND METHOD OF FABRICATING THE SAME
    7.
    发明申请
    TRANSISTOR AND METHOD OF FABRICATING THE SAME 有权
    晶体管及其制造方法

    公开(公告)号：US20150318363A1

    公开(公告)日：2015-11-05

    申请号：US14800251

    申请日：2015-07-15

    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

    Inventor： Sung Haeng CHO ,  Sang-Hee PARK ,  Chi-Sun HWANG

    IPC: H01L29/417 ,  H01L29/08 ,  H01L29/66

    CPC classification number: H01L29/41775 ,  H01L29/0847 ,  H01L29/41733 ,  H01L29/41758 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/786 ,  H01L29/78603 ,  H01L29/7869

    Abstract: Provided is a transistor. The transistor includes: a substrate; a semiconductor layer provided on the substrate and having one side vertical to the substrate and the other side facing the one side; a first electrode extending along the substrate and contacting the one side of the semiconductor layer; a second electrode extending along the substrate and contacting the other side of the semiconductor layer; a conductive wire disposed on the first electrode and spaced from the second electrode; a gate electrode provided on the semiconductor layer; and a gate insulating layer disposed between the semiconductor layer and the gate electrode, wherein the semiconductor layer, the first electrode, and the second electrode have a coplanar.

    Abstract translation: 提供一种晶体管。 晶体管包括：衬底; 半导体层，其设置在所述基板上，并且具有与所述基板垂直的一侧，所述另一侧面向所述一侧; 沿所述基板延伸并接触所述半导体层的一侧的第一电极; 第二电极，沿着衬底延伸并接触半导体层的另一侧; 布置在所述第一电极上并与所述第二电极间隔开的导线; 设置在所述半导体层上的栅电极; 以及设置在所述半导体层和所述栅电极之间的栅绝缘层，其中所述半导体层，所述第一电极和所述第二电极具有共面。

    SRAM DEVICE INCLUDING OXIDE SEMICONDUCTOR
    9.
    发明申请
    SRAM DEVICE INCLUDING OXIDE SEMICONDUCTOR 有权

    公开(公告)号：US20230102625A1

    公开(公告)日：2023-03-30

    申请号：US17529817

    申请日：2021-11-18

    Applicant: Electronics and Telecommunications Research Institute

    Inventor： Sung Haeng CHO ,  Byung-Do YANG ,  Sooji NAM ,  Jaehyun MOON ,  Jae-Eun PI ,  Jae-Min KIM

    IPC: H01L27/11 ,  G11C11/412 ,  G11C11/417

    Abstract: Provided is a static random-access memory (SRAM) device. The SRAM device includes a substrate including a PMOS area, a circuit wiring structure including an insulating layer and a wiring layer alternately stacked on the substrate, wherein the circuit wiring structure includes a first NMOS area and a second NMOS area vertically separated from the PMOS area with the first NMOS area therebetween, a first transistor including a first gate electrode disposed on the PMOS area, source/drain areas formed on the PMOS area on both sides of the first gate electrode, and a first channel connecting the source and drain areas to each other, a second transistor including a second gate electrode disposed in the first NMOS area and a second channel vertically overlapping the second gate electrode, and a third transistor including a third gate electrode disposed in the second NMOS area and a third channel vertically overlapping the third gate electrode, wherein the first channel includes silicon, wherein the second channel and the third channel include an oxide semiconductor.

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