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1.发明申请公开(公告)号：US20200302279A1
公开(公告)日：2020-09-24
申请号：US16813901
申请日：2020-03-10
Inventor： Hyun Kyu YU , Young-Su KWON , JOO HYUN LEE
Abstract: An electronic device includes first to n-th cells (‘n’ is an integer of 2 or more) that receive spatial-temporal input signals that indicate an event unit in a time window, a summation circuit that sums first to n-th cell signals recorded in the first to n-th cells for each of first to m-th unit times (‘m’ is an integer of 2 or more) dividing the time window to generate first to m-th summation signals, and an encoding circuit that compares each of the first to m-th summation signals with a threshold value to encode the spatial-temporal input signals into a code of the event unit.
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公开(公告)号：US20200177195A1
公开(公告)日：2020-06-04
申请号：US16701482
申请日：2019-12-03
Inventor： Young-deuk JEON , MIN-HYUNG CHO , JOO HYUN LEE
Abstract: An analog-to-digital converter includes a capacitor array including capacitors, an amplifier receiving an input current through an input node and integrating the input current, using the capacitor array, in a first mode, a switch array including switches respectively connected to the capacitors, successive approximation logic performing a successive approximation by selectively connecting each of the capacitors to one of a common voltage and a reference voltage through the switches, in a second mode, a comparator comparing the common voltage with an output of the amplifier and output a pulse signal based on the comparison result, a counter counting the pulse signal in the first mode, a register sequentially storing values of the pulse signal, in the second mode, and error correction logic storing an output of the counter as upper bits and an output of the register as lower bits and performing error correction.
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公开(公告)号：US20210303982A1
公开(公告)日：2021-09-30
申请号：US17205433
申请日：2021-03-18
Inventor： Mi Young LEE , Young-deuk JEON , Byung Jo KIM , Ju-Yeob KIM , Jin Kyu KIM , Ki Hyuk PARK , JOO HYUN LEE , MIN-HYUNG CHO
Abstract: Disclosed is a neural network computing device. The neural network computing device includes a neural network accelerator including an analog MAC, a controller controlling the neural network accelerator in one of a first mode and a second mode, and a calibrator that calibrating a gain and a DC offset of the analog MAC. The calibrator includes a memory storing weight data, calibration weight data, and calibration input data, a gain and offset calculator reading the calibration weight data and the calibration input data from the memory, inputting the calibration weight data and the calibration input data to the analog MAC, receiving calibration output data from the analog MAC, and calculating the gain and the DC offset of the analog MAC, and an on-device quantizer reading the weight data, receiving the gain and the DC offset, generating quantized weight data, based on the gain and the DC offset.
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4.发明申请公开(公告)号：US20190289229A1
公开(公告)日：2019-09-19
申请号：US16356788
申请日：2019-03-18
Inventor： Hyun Kyu YU , Sung Weon KANG , Young-Su KWON , JOO HYUN LEE
Abstract: Provided is an image sensor. The image sensor includes a pixel array including pixels arranged along a first direction and a second direction, and partitioned into blocks, a converter configured to convert image signals outputted from the pixels into digital signals based on an image, and an image signal processor configured to add amplitudes of the digital signals belonging to each of the blocks to determine edge blocks among the blocks, compare the amplitudes of the digital signals to determine directions in which direction lines of the edge blocks are directed, and connect the direction lines to extract an edge of the image.
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