中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

43 records (took 0.022 seconds)

    DIGITAL CLOCK AND DATA RECOVERY CIRCUIT AND FEEDBACK LOOP CIRCUIT INCLUDING THE SAME
    1.
    发明申请
    DIGITAL CLOCK AND DATA RECOVERY CIRCUIT AND FEEDBACK LOOP CIRCUIT INCLUDING THE SAME 有权

    公开(公告)号：US20230125872A1

    公开(公告)日：2023-04-27

    申请号：US17881417

    申请日：2022-08-04

    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

    Inventor： Seon-Ho HAN ,  Young-Su KWON

    IPC: H04L7/033 ,  H03L7/08 ,  H03L7/093

    Abstract: Disclosed are a digital CDR circuit and a feedback loop circuit including the same. The digital CDR circuit includes a phase detector that receives an input signal and outputs a phase detection result signal corresponding to a determination result for a sampling time based on the input signal, a charge pump that receives the phase detection result signal and outputs an amplified signal obtained by multiplying the phase detection result signal by a gain, a loop filter that receives the amplified signal and filters the amplified signal to output a filtered signal, and a phase shift control code generator that generates a control signal for controlling a phase of a signal based on the filtered signal, and the input signal includes plural data signals and plural error signals, and the data signals and the error signals are digital signals which are quantized based on a signal magnitude.

    PROCESSOR FOR DETECTING AND PREVENTING RECOGNITION ERROR
    3.
    发明申请
    PROCESSOR FOR DETECTING AND PREVENTING RECOGNITION ERROR 审中-公开

    公开(公告)号：US20200167245A1

    公开(公告)日：2020-05-28

    申请号：US16694913

    申请日：2019-11-25

    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

    Inventor： Jin Ho HAN ,  Young-Su KWON ,  Min-Seok CHOI

    IPC: G06F11/16 ,  G06F11/18

    Abstract: Provided is an image recognition processor. The image recognition processor includes a plurality of nano cores each configured to perform a pattern recognition operation and arranged in rows and columns, an instruction memory configured to provide instructions to the plurality of nano cores in a row unit, a feature memory configured to provide input features to the plurality of nano cores in a row unit, a kernel memory configured to provide a kernel coefficient to the plurality of nano cores in a column unit, and a difference checker configured to receive a result of the pattern recognition operation of each of the plurality of nano cores, detect whether there is an error by referring to the received result, and provide a fault tolerance function that allows an error below a predefined level.

    SEMICONDUCTOR SYSTEM INCLUDING FAULT MANAGER
    4.
    发明申请
    SEMICONDUCTOR SYSTEM INCLUDING FAULT MANAGER 审中-公开

    公开(公告)号：US20190108105A1

    公开(公告)日：2019-04-11

    申请号：US16117403

    申请日：2018-08-30

    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

    Inventor： Jin Ho HAN ,  Min-Seok CHOI ,  Young-Su KWON

    IPC: G06F11/14

    Abstract: Provided is a semiconductor system including: a fault detector configured to obtain fault information related to a fault occurring in a first intellectual property (IP); a fault manager configured to store recovery information providing one or more recovery methods related to the fault information and determine a recovery method for recovering the fault occurring in the first IP among the one or more recovery methods based on the recovery information; and a fault recovery module configured to control the first IP based on the determined recovery method. The determined recovery method involves communication between the first IP and a second IP and the fault occurring in the first IP is recovered based on data delivered according to the communication between the first IP and the second IP.

    DUAL-MODE INSTRUCTION FETCHING APPARATUS AND METHOD
    6.
    发明申请
    DUAL-MODE INSTRUCTION FETCHING APPARATUS AND METHOD 审中-公开
    双模式指令设备和方法

    公开(公告)号：US20140344551A1

    公开(公告)日：2014-11-20

    申请号：US14257067

    申请日：2014-04-21

    Applicant: Electronics and Telecommunications Research Institute

    Inventor： Young-Su KWON

    IPC: G06F9/38

    CPC classification number: G06F9/3806 ,  G06F9/30189 ,  G06F9/3802 ,  G06F9/382 ,  G06F9/3844 ,  G06F9/3873

    Abstract: The dual-mode instruction fetching apparatus includes a mode register, a branch prediction unit, a Program Counter (PC) calculator, an Instruction Queue (IQ), and a fetch multiplexer. The mode register is set to one of normal mode and line mode. The PC calculator accesses a tag in which the address indices of instructions have been stored or a line in which the instructions have been grouped and then outputs an instruction, or accesses only the line and then outputs an instruction depending on the type of set mode. The IQ stores instructions selected by an instruction selector from among the instructions grouped in the line. The fetch multiplexer fetches the instructions stored in the IQ if the normal mode has been set, and fetches instructions read from the line of an instruction cache if the line mode has been set.

    Abstract translation: 双模指令获取装置包括模式寄存器，分支预测单元，程序计数器（PC）计算器，指令队列（IQ）和提取多路复用器。 模式寄存器设置为正常模式和线路模式之一。 PC计算器访问已经存储了指令的地址索引的标签或指令已被分组的行，然后输出指令，或仅访问该行，然后根据设置模式的类型输出指令。 IQ从存储在行中的指令中存储由指令选择器选择的指令。 如果已经设置了正常模式，则提取复用器将获取存储在IQ中的指令，并且如果设置了线路模式，则从指令高速缓存行读取指令。

    DEVICE FOR REORGANIZABLE NEURAL NETWORK COMPUTING
    9.
    发明申请
    DEVICE FOR REORGANIZABLE NEURAL NETWORK COMPUTING 审中-公开

    公开(公告)号：US20190164035A1

    公开(公告)日：2019-05-30

    申请号：US16201871

    申请日：2018-11-27

    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

    Inventor： Young-Su KWON ,  Chan KIM ,  Hyun Mi KIM ,  Jeongmin YANG ,  Chun-Gi LYUH ,  Jaehoon CHUNG ,  Yong Cheol Peter CHO

    IPC: G06N3/04

    Abstract: A reorganizable neural network computing device is provided. The computing device includes a data processing array unit including a plurality of operators disposed at locations corresponding to a row and a column. One or more chaining paths which transfer the first input data from the operator of the first row of the data processing array to the operator of the second row are optionally formed. The plurality of first data input processors of the computing device transfer the first input data for a layer of the neural network to the operators along rows of the data processing array unit, and the plurality of second data input processors of the computing device transfer the second input data to the operators along the columns of the data processing array.

Patent Agency Ranking