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    METHOD AND APPARATUS FOR BEAM MANAGEMENT IN COMMUNICATION SYSTEM
    1.
    发明申请
    METHOD AND APPARATUS FOR BEAM MANAGEMENT IN COMMUNICATION SYSTEM 有权

    公开(公告)号：US20230051098A1

    公开(公告)日：2023-02-16

    申请号：US17880222

    申请日：2022-08-03

    Applicant: Electronics and Telecommunications Research Institute

    Inventor： Jung Bin KIM ,  Won Jin BYUN ,  Joon Gyu RYU

    IPC: H04W56/00 ,  H04W76/20

    Abstract: An operation method of a terminal in a communication system may comprise: receiving, from a satellite, transmission timing information including information on a first transmission timing of a first SSB of each of at least one local cell and information on second transmission timings of second SSBs of sub-cells belonging to each of the at least one local cell; identifying the first transmission timing of the first SSB and the second transmission timings of the second SSBs based on the transmission timing information; attempting to receive the second SSBs when the first SSB is received at the first transmission timing; acquiring cell access information from the second SSBs by receiving the second SSBs; and accessing the satellite by using the acquired cell access information.

    METHOD AND SYSTEM FOR COMPENSATING FOR RETURN LINK RAIN ATTENUATION IN SATELLITE COMMUNICATION SYSTEM
    3.
    发明申请
    METHOD AND SYSTEM FOR COMPENSATING FOR RETURN LINK RAIN ATTENUATION IN SATELLITE COMMUNICATION SYSTEM 审中-公开
    用于补偿卫星通信系统中返回链路衰减的方法和系统

    公开(公告)号：US20160242066A1

    公开(公告)日：2016-08-18

    申请号：US15040033

    申请日：2016-02-10

    Applicant: Electronics and Telecommunications Research Institute

    Inventor： Joon Gyu RYU

    IPC: H04W28/02 ,  H04B1/10 ,  H04B7/185

    CPC classification number: H04W28/0236 ,  H04B7/18513 ,  H04L1/00 ,  H04L1/0003 ,  H04L1/0009 ,  H04L1/0026 ,  H04L47/38

    Abstract: A method for overcoming rain attenuation in a return link in a satellite communication system is provided. The method may include periodically receiving channel state information from a terminal, estimating a signal-to-noise ratio (SNR) based on the channel state information, determining, based on the estimated SNR, whether rain attenuation is to be compensated for, analyzing the channel state information and determining a rain attenuation compensation scheme, and transmitting an operating mode change command corresponding to the rain attenuation compensation scheme to the terminal.

    Abstract translation: 提供了一种用于在卫星通信系统中的返回链路中克服雨衰的方法。 该方法可以包括周期性地从终端接收信道状态信息，基于信道状态信息来估计信噪比（SNR），基于所估计的SNR来确定雨衰是否得到补偿，分析 信道状态信息，并确定雨衰补偿方案，并向终端发送与雨衰补偿方案对应的工作模式改变命令。

    METHOD AND APPARATUS FOR TRANSMITTING SIGNALS USING FREQUENCY HOPPING
    5.
    发明公开
    METHOD AND APPARATUS FOR TRANSMITTING SIGNALS USING FREQUENCY HOPPING 审中-公开

    公开(公告)号：US20240214115A1

    公开(公告)日：2024-06-27

    申请号：US18396528

    申请日：2023-12-26

    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

    Inventor： Soo Yeob JUNG ,  Mi Kyung OH ,  Joon Gyu RYU ,  Sang Jae LEE

    IPC: H04L1/00 ,  H04L5/00 ,  H04L27/26

    CPC classification number: H04L1/0061 ,  H04L1/0071 ,  H04L5/0012 ,  H04L27/2605

    Abstract: A transmission device in a satellite IoT system may comprise: a CRC value generator that receives first data and generates and outputs a payload CRC value; a forward error correction encoder that receives second data consisting of the first data and the payload CRC value from the CRC value generator, and performs forward error correction coding on the second data; an interleaver that receives third data consisting of the forward error correction coded first data and the payload CRC value from the forward error correction encoder, and outputs interleaved payload blocks by performing cyclic shifts on the forward error correction coded first data based on offsets; and a frequency hopping unit that receives the interleaved payload blocks from the interleaver, and generates and transmits payload blocks frequency-hopped according to a hopping sequence.

    PHASE LOCKED LOOP (PLL) APPARATUS AND OPERATING METHOD OF PLL APPARATUS
    7.
    发明申请
    PHASE LOCKED LOOP (PLL) APPARATUS AND OPERATING METHOD OF PLL APPARATUS 审中-公开
    PLL装置的锁相环（PLL）装置和操作方法

    公开(公告)号：US20150171874A1

    公开(公告)日：2015-06-18

    申请号：US14561011

    申请日：2014-12-04

    Applicant: Electronics and Telecommunications Research Institute

    Inventor： Joon Gyu RYU

    IPC: H03L7/099 ,  H03L7/087 ,  H03L7/093

    CPC classification number: H03L7/23 ,  H03L7/185

    Abstract: Provided are a phase locked loop (PLL) apparatus and an operating method of the PLL apparatus including a PLL unit to provide a fixed frequency signal, a converter to convert, using the fixed frequency signal, a frequency of a first signal oscillated by a first voltage-controlled oscillator (VCO) based on a first control voltage, a first frequency divider to divide the converted frequency of the first signal, and a first phase comparator to compare the divided frequency of the first signal to an input first reference frequency and detect a first phase difference, wherein the first VCO may adjust the first control voltage based on the detected first phase difference to equalize the divided frequency of the first signal to the first reference frequency.

    Abstract translation: 提供了一种锁相环（PLL）装置和PLL装置的操作方法，该PLL装置包括提供固定频率信号的PLL单元，使用固定频率信号转换由第一信号振荡的第一信号的频率的转换器 基于第一控制电压的压控振荡器（VCO），分频第一信号的转换频率的第一分频器和第一相位比较器，用于将第一信号的分频与输入的第一参考频率进行比较，并检测 第一相位差，其中第一VCO可以基于检测到的第一相位差来调整第一控制电压，以将第一信号的分频为第一参考频率。

    SYSTEM AND METHOD FOR SYNCHRONIZATION BETWEEN DIGITAL-TO-ANALOG CONVERTERS (DACs) FOR HIGH SPEED SIGNAL PROCESSING
    8.
    发明申请
    SYSTEM AND METHOD FOR SYNCHRONIZATION BETWEEN DIGITAL-TO-ANALOG CONVERTERS (DACs) FOR HIGH SPEED SIGNAL PROCESSING 有权
    用于高速信号处理的数字到模拟转换器（DAC）之间的同步的系统和方法

    公开(公告)号：US20150061909A1

    公开(公告)日：2015-03-05

    申请号：US14301753

    申请日：2014-06-11

    Applicant: Electronics and Telecommunications Research Institute

    Inventor： Soo Yeob JUNG ,  Pan Soo KIM ,  Joon Gyu RYU ,  Deock Gil OH

    IPC: H03M1/66

    CPC classification number: H03M1/662 ,  H03M1/0624 ,  H03M1/66

    Abstract: Provided is a system and method for synchronization between digital-to-analog converters (DAC) for high speed signal processing. A synchronization method of a multi-DAC apparatus may include: inputting a clock to a multiplexer (MUX) DAC; dividing the clock into a first clock and a second clock; transferring a phase difference between the first clock and the second clock to a D flip-flop; and synchronizing the first clock and the second clock by processing the phase difference.

    Abstract translation: 提供了用于高速信号处理的数模转换器（DAC）之间的同步的系统和方法。 多DAC装置的同步方法可以包括：将时钟输入到多路复用器（MUX）DAC; 将时钟分为第一时钟和第二时钟; 将第一时钟和第二时钟之间的相位差传送到D触发器; 以及通过处理所述相位差来同步所述第一时钟和所述第二时钟。

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