公开(公告)号：US09735788B2

公开(公告)日：2017-08-15

申请号：US15185438

申请日：2016-06-17

Applicant: Electronics and Telecommunications Research Institute

Inventor： Ja Yol Lee ,  Minjae Lee ,  Cheon Soo Kim ,  Jaehyun Kang ,  Junsoo Ko

IPC: H03L7/18 ,  H03L1/00 ,  H03L7/099 ,  H03L7/093 ,  H03K5/135 ,  H03K5/00

CPC classification number: H03K5/135 ,  H03K2005/00052 ,  H03L7/081 ,  H03L2207/50

Abstract: Provided is a phase locked loop (PLL) that generates an output clock signal corresponding to a reference clock signal, the PLL including a first phase interpolator configured to generate a first interpolator clock signal that has a first time delay from the output clock signal and a second phase interpolator configured to generate a second interpolator clock signal that has a second time delay from the output clock signal. The PLL controls a frequency of the output clock signal based on a multiplexing the first interpolator clock signal and the second interpolator clock signal.