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公开(公告)号：US09654119B2
公开(公告)日：2017-05-16
申请号：US15184113
申请日：2016-06-16
Inventor： Ja Yol Lee , Minjae Lee , Cheon Soo Kim , Jaehyun Kang , Minuk Heo
Abstract: Provided is a phase locked loop (PLL) that generates an output clock signal corresponding to a reference clock signal. The phase locked loop (PLL) includes a divider configured to divide the output clock signal to generate a divided clock signal, a time-pulse converter configured to generate a time-pulse conversion signal that has a pulse corresponding to a phase difference between the reference clock signal and the divided clock signal, and a digitally controlled oscillator including an LC resonance circuit for generating the output clock signal and configured to control a frequency of the output clock signal that is determined to correspond to a time constant of the LC resonance circuit according to the time-pulse conversion signal, wherein a sustainment time of changed capacitance is continuously controlled according to a change in the phase difference between the reference clock signal and the divided clock signal.
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公开(公告)号：US20130321198A1
公开(公告)日：2013-12-05
申请号：US13759333
申请日：2013-02-05
Inventor： Pil Jae PARK , Cheon Soo Kim , Hyun Kyu Yu
IPC: G01S13/02
CPC classification number: G01S13/02 , G01S7/032 , G01S13/726 , G01S13/878 , G01S13/92
Abstract: A MIMO radar system includes one or more receivers and transmitters. Any one of the one or more transmitters provides a reference signal for injection-locking. The MIMO radar system generates multiple signals having phase and frequency which are injection-locked to those of the reference signal.
Abstract translation: MIMO雷达系统包括一个或多个接收机和发射机。 一个或多个发射器中的任何一个提供用于注射锁定的参考信号。 MIMO雷达系统产生具有相位和频率的多个信号，其被注入锁定到参考信号的信号。
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Patent Agency Ranking
公开(公告)号：US09013216B2
公开(公告)日：2015-04-21
申请号：US14028707
申请日：2013-09-17
Inventor： Hyun Ho Boo , Byung Hun Min , Duong Quoc Hoang , Cheon Soo Kim , Hyun Kyu Yu
Abstract: Disclosed is a digital phase-locked-loop including: a time-to-digital converter (TDC) configured to output a digital bit based on an input clock and a reference clock, in which the TDC includes: a first arbiter group configured to compensate for a phase difference between the input clock and the reference clock with a first average offset and output a first logic value; a second arbiter group configured to compensate for a phase difference between the input clock and the reference clock with a second average offset and output a second logic value; and a signal processor configured to output the digital bit based on the first and second logic values.
Abstract translation: 公开了一种数字锁相环，包括：时间数字转换器（TDC），被配置为基于输入时钟和参考时钟输出数字位，其中TDC包括：第一仲裁器组，其被配置为补偿 对于具有第一平均偏移的输入时钟和参考时钟之间的相位差，并输出第一逻辑值; 第二仲裁器组，被配置为用第二平均偏移补偿所述输入时钟和所述参考时钟之间的相位差，并输出第二逻辑值; 以及信号处理器，被配置为基于第一和第二逻辑值输出数字位。
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公开(公告)号：US10044385B2
公开(公告)日：2018-08-07
申请号：US15074881
申请日：2016-03-18
Inventor： Dong Woo Kang , Cheon Soo Kim , Jang Hong Choi
Abstract: Provided is a transmitter. The transmitter includes a signal combiner configured to amplify a first differential radio frequency (RF) signal modulated to be transmitted through a first frequency band and a second differential RF signal modulated to be transmitted through a second frequency band non-adjacent to the first frequency band and summate the amplified first differential RF signal and the amplified second differential RF signal in a current mode to generate an RF signal and a power amplifier configured to amplify the generated RF signal.
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公开(公告)号：US09735788B2
公开(公告)日：2017-08-15
申请号：US15185438
申请日：2016-06-17
Inventor： Ja Yol Lee , Minjae Lee , Cheon Soo Kim , Jaehyun Kang , Junsoo Ko
CPC classification number: H03K5/135 , H03K2005/00052 , H03L7/081 , H03L2207/50
Abstract: Provided is a phase locked loop (PLL) that generates an output clock signal corresponding to a reference clock signal, the PLL including a first phase interpolator configured to generate a first interpolator clock signal that has a first time delay from the output clock signal and a second phase interpolator configured to generate a second interpolator clock signal that has a second time delay from the output clock signal. The PLL controls a frequency of the output clock signal based on a multiplexing the first interpolator clock signal and the second interpolator clock signal.
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公开(公告)号：US09780891B2
公开(公告)日：2017-10-03
申请号：US15229950
申请日：2016-08-05
Inventor： Ik Soo Eo , Sang-Kyun Kim , Cheon Soo Kim , Jang Hong Choi
CPC classification number: H04B17/14 , H04B17/0085 , H04B17/104
Abstract: A method and device for calibrating a DC offset and an I-Q imbalance component of an RF transceiver, the method including inputting a test signal into a transmitter, and converting the test signal into an analogue test signal; converting the analogue test signal using a transmitting mixer; sub-sampling a signal output from the transmitting mixer; and computing a DC offset calibrating constant number and an I-Q imbalance calibrating constant number from a sub-sampled signal.
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公开(公告)号：US09705515B1
公开(公告)日：2017-07-11
申请号：US15273764
申请日：2016-09-23
Inventor： Ja Yol Lee , Min Jae Lee , Cheon Soo Kim , Min Uk Heo
CPC classification number: H03L7/0991 , H03L7/081 , H03L7/085 , H03L7/091 , H03L7/093 , H03L7/18 , H03L7/183
Abstract: Provided herein is a digital PLL, which can minimize spurious noise. The digital PLL includes a digital controlled oscillator configured to generate an output oscillation signal in response to a digital code, a phase modulation unit configured to perform phase interpolation on the output oscillation signal in response to a phase control code, a TDC configured to generate an error code using a time difference between a reference clock signal and a modulated clock signal, an error detection unit configured to generate a delay code required to compensate for a phase shift error in response to the phase control code and the error code, a delay unit configured to delay at least one of the reference clock signal and the modulated clock signal and provide a delayed clock signal, and a first decoder configured to control the delay unit in response to the delay code.
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