InGaP pHEMT device for power amplifier operation over wide temperature range
    1.
    发明申请
    InGaP pHEMT device for power amplifier operation over wide temperature range 审中-公开
    InGaP pHEMT器件用于宽温度范围内的功率放大器工作

    公开(公告)号:US20050104087A1

    公开(公告)日:2005-05-19

    申请号:US10881162

    申请日:2004-06-30

    CPC分类号: H03F1/301 H01L29/7785

    摘要: In one embodiment, a semiconductor device (500) includes a buffer layer (504) formed over a substrate (502). An AlxGa1-xAs layer (506) is formed over the buffer layer (504) and has a first doped region (508) formed therein. An InxGa1-xAs channel layer (512) is formed over the AlxGa1-xAs layer (506). An InxGa1-xP barrier layer (518) is formed over the InxGa1-xAs channel layer (512), the InxGa1-xP layer (518) has a second doped region formed therein. A control electrode (526) is formed over the InxGa1-xP layer (518). An undoped GaAs layer (520) is formed over the InxGa1-xP layer (518) adjacent to the control electrode (526). A doped GaAs layer (524) is formed over the undoped GaAs layer (520) and on opposite sides of the control electrode (526) and provides first and second current electrodes. When used to amplify a digital modulation signal, the semiconductor device (500) maintains linear operation over a wide temperature range.

    摘要翻译: 在一个实施例中,半导体器件(500)包括形成在衬底(502)上的缓冲层(504)。 在缓冲层(504)之上形成Al x Ga 1-x As层(506),并且在其中形成有第一掺杂区域(508)。 在Al x Ga 1-x 上形成一个In 1 / x Ga 1-x As As沟道层(512) >作为层(506)。 在In 1 / x Ga 1-x 作为沟道层(512),In 1 / x Ga 1-x P层(518)具有形成在其中的第二掺杂区域。 控制电极(526)形成在In 1 x 1 Ga 1-x P层(518)上。 在与控制电极(526)相邻的In 1 x 1 Ga 1-x P P层(518)上形成未掺杂的GaAs层(520)。 在未掺杂的GaAs层(520)上和控制电极(526)的相对侧上形成掺杂GaAs层(524),并提供第一和第二电流电极。 当用于放大数字调制信号时,半导体器件(500)在宽的温度范围内保持线性操作。

    pHEMT with barrier optimized for low temperature operation
    2.
    发明申请
    pHEMT with barrier optimized for low temperature operation 有权
    pHEMT具有针对低温操作优化的阻挡层

    公开(公告)号:US20060220062A1

    公开(公告)日:2006-10-05

    申请号:US11100095

    申请日:2005-04-05

    IPC分类号: H01L29/739

    CPC分类号: H01L29/7785

    摘要: In one embodiment, a semiconductor device (500) includes a buffer layer (504) formed over a substrate (502). An AlxGa1-xAs layer (506) is formed over the buffer layer (504) and has a first doped region (508) formed therein. An InxGa1-xAs channel layer (512) is formed over the AlxGa1-xAs layer (506). An AlxGa1-xAs layer (518) is formed over the InxGa1-xAs channel layer (512), and the AlxGa1-xAs layer (518) has a second doped region formed therein. A GaAs layer (520) having a first recess is formed over the AlxGa1-xAs layer (518). A control electrode (526) is formed over the AlxGa1-xAs layer (518). A doped GaAs layer (524) is formed over the undoped GaAs layer (520) and on opposite sides of the control electrode (526) and provides first and second current electrodes. When used to amplify a digital modulation signal, the semiconductor device (500) maintains linear operation over a wide temperature range.

    摘要翻译: 在一个实施例中,半导体器件(500)包括形成在衬底(502)上的缓冲层(504)。 在缓冲层(504)之上形成Al x Ga 1-x As层(506),并且在其中形成有第一掺杂区域(508)。 在Al x Ga 1-x 上形成一个In 1 / x Ga 1-x As As沟道层(512) >作为层(506)。 在In 1 x 1 Ga 1-x N上形成Al x Ga 1-x As层(518) 作为沟道层(512)和Al x Ga 1-x As层(518)具有形成在其中的第二掺杂区域。 具有第一凹陷的GaAs层(520)形成在Al 1 Ga 1-x As层(518)上。 控制电极(526)形成在Al 1 Ga 1-x As As层(518)上。 在未掺杂的GaAs层(520)上和控制电极(526)的相对侧上形成掺杂GaAs层(524),并提供第一和第二电流电极。 当用于放大数字调制信号时,半导体器件(500)在宽的温度范围内保持线性操作。

    Recessed semiconductor device
    3.
    发明申请
    Recessed semiconductor device 有权
    嵌入式半导体器件

    公开(公告)号:US20060043416A1

    公开(公告)日:2006-03-02

    申请号:US10925855

    申请日:2004-08-25

    IPC分类号: H01L31/0328

    摘要: A semiconductor structure includes a first semiconductor layer, a second semiconductor layer over the first semiconductor layer, a third semiconductor layer over the second semiconductor layer, and a fourth semiconductor layer over the third semiconductor layer. A first conductive portion is coupled to the first semiconductor layer, and a second conductive portion is formed over the first semiconductor layer.

    摘要翻译: 半导体结构包括第一半导体层,第一半导体层上的第二半导体层,第二半导体层上的第三半导体层以及第三半导体层上的第四半导体层。 第一导电部分耦合到第一半导体层,并且在第一半导体层上形成第二导电部分。