公开(公告)号：US08922025B2

公开(公告)日：2014-12-30

申请号：US13913985

申请日：2013-06-10

Applicant: Elpida Memory, Inc.

Inventor： Kazuo Ono ,  Riichiro Takemura ,  Takamasa Suzuki ,  Kazuhiko Kajigaya ,  Akira Kotabe ,  Yoshimitsu Yanagawa

IPC: H01L23/64 ,  H01L23/66 ,  H01L23/48 ,  H01L23/528 ,  H01L23/498

CPC classification number: H01L23/5226 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/528 ,  H01L23/5286 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/16146 ,  H01L2924/0002 ,  H01L2924/00

Abstract: There is provided a semiconductor device which includes a plurality of first through-substrate vias that are used to supply power from a first power supply and that penetrate through a substrate structure, and a plurality of second through-substrate vias that are used to supply power from a second power supply different from the first power supply and that penetrate through a substrate structure. The semiconductor device also includes a through-substrate via string composed by the first and second through-substrate vias, in which the first through-substrate vias are located adjacent to one another and the second through-substrate vias are also located adjacent to one another. The through-substrate via string is disposed in the substrate structure for extending in a first direction.

Abstract translation: 提供了一种半导体器件，其包括多个用于从第一电源供电并穿透衬底结构的第一贯穿衬底通孔以及用于供电的多个第二贯穿衬底通孔 来自与第一电源不同的第二电源，并且穿过衬底结构。 该半导体器件还包括由第一和第二贯穿衬底通孔组成的贯穿衬底通孔串，其中第一贯穿衬底通孔彼此相邻定位，并且第二贯穿衬底通孔也彼此相邻地定位 。 贯通基板通孔串设置在基板结构中，用于沿第一方向延伸。

公开(公告)号：US08964478B2

公开(公告)日：2015-02-24

申请号：US13901025

申请日：2013-05-23

Applicant: Elpida Memory, Inc.

Inventor： Shinichi Takayama ,  Akira Kotabe ,  Kiyoo Itoh ,  Tomonori Sekiguchi

IPC: G11C11/34 ,  G11C7/08 ,  G11C11/4091 ,  G11C11/4094

CPC classification number: G11C7/08 ,  G11C11/4091 ,  G11C11/4094

Abstract: A semiconductor device includes a sense amplifier circuit. The sense amplifier circuit includes a cross-coupled first transistor and second transistor that perform amplification. The sources of the cross-coupled transistors are respectively connected in series with a third transistor and a fourth transistor, and electrical current supply capability of the third and fourth transistors is controlled by a control voltage given to control electrodes of the third and fourth transistors. In a data retaining period, a minimum sub-threshold current necessary for retaining the data is flowed to the third and fourth transistors according to the control voltage, and bit line potential is maintained.

Abstract translation: 半导体器件包括读出放大器电路。 读出放大器电路包括执行放大的交叉耦合的第一晶体管和第二晶体管。 交叉耦合晶体管的源极分别与第三晶体管和第四晶体管串联连接，并且通过施加到第三和第四晶体管的控制电极的控制电压来控制第三和第四晶体管的电流供应能力。 在数据保持期间，保持数据所需的最小子阈值电流根据控制电压流向第三和第四晶体管，并保持位线电位。