公开(公告)号：US20140169111A1

公开(公告)日：2014-06-19

申请号：US14177210

申请日：2014-02-10

Applicant: Elpida Memory, Inc.

Inventor： Kazuhiko Kajigaya ,  Tomonori Sekiguchi ,  Kazuo Ono

IPC: G11C11/4076 ,  G11C11/409

CPC classification number: G11C11/409 ,  G11C5/02 ,  G11C5/06 ,  G11C7/1039 ,  G11C7/18 ,  G11C11/4076

Abstract: A method for carrying out read and write operations in a synchronous memory device having a shared I/O, includes receiving a read command directed to a first internal memory bank during a first timeslot, activating the first internal memory bank to access read data at a read address requested by the read command, receiving a write command directed to a second internal memory bank during a second timeslot later than the first timeslot, determining whether a data collision between the read data for output to the shared I/O with normal read latency and write data to be received on the shared I/O with normal write latency would occur, and receiving the write data on the shared I/O with the normal write latency during a third timeslot later than the second timeslot.

Abstract translation: 一种用于在具有共享I / O的同步存储器件中执行读写操作的方法，包括在第一时隙期间接收指向第一内部存储体的读取命令，激活第一内部存储体以访问读取数据 读取命令所请求的读取地址，在比第一时隙晚的第二时隙期间接收指向第二内部存储体的写入命令，确定用于输出到具有正常读取延迟的共享I / O的读取数据之间的数据冲突 并且将发生在具有正常写入延迟的共享I / O上接收的数据，并且在比第二时隙晚的第三个时隙期间以正常写入延迟在共享I / O上接收写入数据。

公开(公告)号：US20140092691A1

公开(公告)日：2014-04-03

申请号：US13800935

申请日：2013-03-13

Applicant: Elpida Memory, Inc.

Inventor： Kazuhiko Kajigaya

IPC: G11C11/4093 ,  G11C11/4091

CPC classification number: G11C11/4093 ,  G11C5/025 ,  G11C7/08 ,  G11C7/1051 ,  G11C7/1069 ,  G11C11/4091 ,  G11C11/4096 ,  G11C2207/005

Abstract: A semiconductor includes a memory cell array including a plurality of memory cells. A first amplifier produces, when activated, a first data signal related to data stored in a selected first one of the memory cells. A first transistor is between the output node of the first amplifier and a first data line and is turned ON in response to a first selection signal to convey the first data signal from the first amplifier onto the first data line. A second amplifier is coupled to the first data line and amplifies, when activated, the first data signal, and is further coupled to the first signal line and activated in response to a first activation signal that is transferred through a first signal line. A second transistor is coupled to the first signal line and is turned ON in response to the first selection signal to the first signal line.

Abstract translation: 半导体包括包括多个存储单元的存储单元阵列。 第一放大器当被激活时产生与存储在所选择的第一个存储单元中的数据相关的第一数据信号。 第一晶体管位于第一放大器的输出节点和第一数据线之间，并且响应于第一选择信号而导通，以将第一数据信号从第一放大器传送到第一数据线上。 第二放大器耦合到第一数据线，并且当被激活时放大第一数据信号，并且进一步耦合到第一信号线并且响应于通过第一信号线传送的第一激活信号被激活。 第二晶体管耦合到第一信号线，并且响应于到第一信号线的第一选择信号而导通。

公开(公告)号：US08982652B2

公开(公告)日：2015-03-17

申请号：US13675431

申请日：2012-11-13

Applicant: Elpida Memory, Inc.

Inventor： Kazuhiko Kajigaya ,  Soichiro Yoshida ,  Yasutoshi Yamada

IPC: G11C7/02 ,  G11C7/06 ,  G11C11/4091 ,  G11C5/14 ,  G11C7/10 ,  G11C7/00

CPC classification number: G11C7/06 ,  G11C5/147 ,  G11C7/065 ,  G11C7/067 ,  G11C7/1087 ,  G11C11/4091

Abstract: A single-ended sense amplifier circuit of the invention comprises first and second MOS transistors and first and second precharge circuits. The first MOS transistor drives the bit line to a predetermined voltage and switches connection between the bit line and a sense node and the second MOS transistor whose gate is connected to the sense node amplifies the signal via the first MOS transistor. The first precharge circuit precharges the bit line to a first potential and the second precharge circuit precharges the sense node to a second potential. Before sensing operation, the bit line is driven to the predetermined voltage when the above gate voltage is controlled to decrease. The predetermined voltage is appropriately set so that a required voltage difference at the sense node between high and low levels can be obtained near a changing point between charge transfer/distributing modes.

Abstract translation: 本发明的单端读出放大器电路包括第一和第二MOS晶体管以及第一和第二预充电电路。 第一MOS晶体管将位线驱动到预定电压并且切换位线和感测节点之间的连接，并且栅极连接到感测节点的第二MOS晶体管经由第一MOS晶体管放大信号。 第一预充电电路将位线预充电到第一电位，而第二预充电电路将感测节点预充电到第二电位。 在感测操作之前，当控制上述栅极电压降低时，位线被驱动到预定电压。 适当地设定预定电压，使得可以在电荷转移/分配模式之间的变化点附近获得在高电平和低电平之间的感测节点处的所需电压差。

公开(公告)号：US08717805B2

公开(公告)日：2014-05-06

申请号：US13862221

申请日：2013-04-12

Applicant: Elpida Memory, Inc.

Inventor： Kazuhiko Kajigaya

IPC: G11C11/00

CPC classification number: G11C14/00

Abstract: A semiconductor random access memory device includes a memory cell including a resistor whose resistance varies by formation and disappearance of a filament due to an oxidation-reduction reaction of metal ions, a memory area configured to include a first memory area operable in a nonvolatile mode in which a stored content thereof is not lost by a power-off event, and a second memory area operable in a volatile mode in which the stored content thereof is lost by the power-off event, each of the first memory area and the second memory area including the plurality of the memory cells, a register circuit that stores information including a first address information indicating the first memory area, and a second address information indicating the second memory area, and a control circuit that controls the nonvolatile mode, and the volatile mode, with reference to the information stored in the register circuit.

Abstract translation: 一种半导体随机存取存储器件包括：存储单元，其包括电阻器，其电阻随着金属离子的氧化还原反应而由丝的形成和消失而变化，存储区域被配置为包括以非易失性模式操作的第一存储区域 其存储的内容不被电源关闭事件丢失;以及第二存储区域，其中存储的内容由电源关闭事件丢失的易失性模式中可操作，第一存储区域和第二存储器 包括多个存储单元的区域，存储包括指示第一存储区域的第一地址信息的信息的寄存器电路和指示第二存储区域的第二地址信息，以及控制非易失性模式的控制电路， 模式，参考存储在寄存器电路中的信息。

公开(公告)号：US08477552B2

公开(公告)日：2013-07-02

申请号：US13716539

申请日：2012-12-17

Applicant: Elpida Memory, Inc.

Inventor： Kazuhiko Kajigaya ,  Soichiro Yoshida

IPC: G11C7/00

CPC classification number: G11C7/00 ,  G11C7/02 ,  G11C7/12 ,  G11C8/08 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4097

Abstract: A semiconductor memory device comprises a memory cell array, first and second bit lines, first and second amplifiers, and a sense amplifier control circuit. An amplifying element in the first sense amplifier amplifiers the signal of the first bit line and converts it into an output current. The second bit line is selectively connected to the first bit line via the first sense amplifier. A signal voltage decision unit in the second sense amplifier determines the signal level of the second bit line being supplied with the output current. The sense amplifier control circuit controls connection between the amplifying element and the unit in accordance with a determination timing, which switches the above connection from a connected state to a disconnected state at a first timing in a normal operation and switches in the same manner at a delayed second timing in a refresh operation.

Abstract translation: 半导体存储器件包括存储单元阵列，第一和第二位线，第一和第二放大器以及读出放大器控制电路。 第一读出放大器中的放大元件放大第一位线的信号并将其转换为输出电流。 第二位线经由第一读出放大器选择性地连接到第一位线。 第二读出放大器中的信号电压判定单元确定被提供有输出电流的第二位线的信号电平。 读出放大器控制电路根据在正常操作中的第一定时将上述连接从连接状态切换到断开状态的确定定时来控制放大元件与单元之间的连接，并以相同的方式在一个 在刷新操作中延迟第二定时。

公开(公告)号：US08982645B2

公开(公告)日：2015-03-17

申请号：US13800935

申请日：2013-03-13

Applicant: Elpida Memory, Inc.

Inventor： Kazuhiko Kajigaya

IPC: G11C11/4093 ,  G11C11/4091 ,  G11C5/02 ,  G11C7/08 ,  G11C7/10 ,  G11C11/4096

CPC classification number: G11C11/4093 ,  G11C5/025 ,  G11C7/08 ,  G11C7/1051 ,  G11C7/1069 ,  G11C11/4091 ,  G11C11/4096 ,  G11C2207/005

Abstract: A semiconductor includes a memory cell array including a plurality of memory cells. A first amplifier produces, when activated, a first data signal related to data stored in a selected first one of the memory cells. A first transistor is between the output node of the first amplifier and a first data line and is turned ON in response to a first selection signal to convey the first data signal from the first amplifier onto the first data line. A second amplifier is coupled to the first data line and amplifies, when activated, the first data signal, and is further coupled to the first signal line and activated in response to a first activation signal that is transferred through a first signal line. A second transistor is coupled to the first signal line and is turned ON in response to the first selection signal to the first signal line.

Abstract translation: 半导体包括包括多个存储单元的存储单元阵列。 第一放大器当被激活时产生与存储在所选择的第一个存储单元中的数据相关的第一数据信号。 第一晶体管位于第一放大器的输出节点和第一数据线之间，并且响应于第一选择信号而导通，以将第一数据信号从第一放大器传送到第一数据线上。 第二放大器耦合到第一数据线，并且当被激活时放大第一数据信号，并且进一步耦合到第一信号线并且响应于通过第一信号线传送的第一激活信号被激活。 第二晶体管耦合到第一信号线，并且响应于到第一信号线的第一选择信号而导通。

公开(公告)号：US08976612B2

公开(公告)日：2015-03-10

申请号：US13666177

申请日：2012-11-01

Applicant: Elpida Memory, Inc.

Inventor： Kazuhiko Kajigaya ,  Soichiro Yoshida ,  Yasutoshi Yamada

IPC: G11C7/02 ,  G11C7/00 ,  G11C7/06 ,  G11C11/4091 ,  G11C5/14 ,  G11C7/10

CPC classification number: G11C7/06 ,  G11C5/147 ,  G11C7/065 ,  G11C7/067 ,  G11C7/1087 ,  G11C11/4091

Abstract: A single-ended sense amplifier circuit of the invention comprises first and second MOS transistors and first and second precharge circuits. The first MOS transistor drives the bit line to a predetermined voltage and switches connection between the bit line and a sense node and the second MOS transistor whose gate is connected to the sense node amplifies the signal via the first MOS transistor. The first precharge circuit precharges the bit line to a first potential and the second precharge circuit precharges the sense node to a second potential. Before sensing operation, the bit line is driven to the predetermined voltage when the above gate voltage is controlled to decrease. The predetermined voltage is appropriately set so that a required voltage difference at the sense node between high and low levels can be obtained near a changing point between charge transfer/distributing modes.

公开(公告)号：US08922025B2

公开(公告)日：2014-12-30

申请号：US13913985

申请日：2013-06-10

Applicant: Elpida Memory, Inc.

Inventor： Kazuo Ono ,  Riichiro Takemura ,  Takamasa Suzuki ,  Kazuhiko Kajigaya ,  Akira Kotabe ,  Yoshimitsu Yanagawa

IPC: H01L23/64 ,  H01L23/66 ,  H01L23/48 ,  H01L23/528 ,  H01L23/498

CPC classification number: H01L23/5226 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/528 ,  H01L23/5286 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/16146 ,  H01L2924/0002 ,  H01L2924/00

Abstract: There is provided a semiconductor device which includes a plurality of first through-substrate vias that are used to supply power from a first power supply and that penetrate through a substrate structure, and a plurality of second through-substrate vias that are used to supply power from a second power supply different from the first power supply and that penetrate through a substrate structure. The semiconductor device also includes a through-substrate via string composed by the first and second through-substrate vias, in which the first through-substrate vias are located adjacent to one another and the second through-substrate vias are also located adjacent to one another. The through-substrate via string is disposed in the substrate structure for extending in a first direction.

Abstract translation: 提供了一种半导体器件，其包括多个用于从第一电源供电并穿透衬底结构的第一贯穿衬底通孔以及用于供电的多个第二贯穿衬底通孔 来自与第一电源不同的第二电源，并且穿过衬底结构。 该半导体器件还包括由第一和第二贯穿衬底通孔组成的贯穿衬底通孔串，其中第一贯穿衬底通孔彼此相邻定位，并且第二贯穿衬底通孔也彼此相邻地定位 。 贯通基板通孔串设置在基板结构中，用于沿第一方向延伸。

公开(公告)号：US20140056063A1

公开(公告)日：2014-02-27

申请号：US14065286

申请日：2013-10-28

Applicant: ELPIDA MEMORY, INC.

Inventor： Kazuhiko Kajigaya

IPC: G11C7/12

CPC classification number: G11C7/12 ,  G11C7/067 ,  G11C7/18 ,  G11C27/028

Abstract: A method includes performing a read operation on a memory cell of a device including a sensing line, a bit line coupled to the memory cell, a first transistor having a source-drain path coupled between the sensing line and the bit line, and a second transistor having a gate coupled to sense the sensing line, the performing including providing a gate of the first transistor with a first voltage, providing the sensing line with a second voltage, and providing the bit line with a third voltage, the third voltage being independent from the second voltage.

Abstract translation: 一种方法包括对包括感测线，耦合到存储单元的位线，耦合在感测线和位线之间的源极 - 漏极路径的第一晶体管的器件的存储器单元执行读取操作，以及第二 晶体管具有耦合以感测感测线的栅极，所述执行包括提供第一晶体管的栅极具有第一电压，为感测线提供第二电压，以及为位线提供第三电压，第三电压是独立的 从第二电压。

公开(公告)号：US20130315018A1

公开(公告)日：2013-11-28

申请号：US13675431

申请日：2012-11-13

Applicant: ELPIDA MEMORY, INC.

Inventor： Kazuhiko Kajigaya ,  Soichiro YOSHIDA ,  Yasutoshi YAMADA

IPC: G11C7/06

CPC classification number: G11C7/06 ,  G11C5/147 ,  G11C7/065 ,  G11C7/067 ,  G11C7/1087 ,  G11C11/4091

Abstract: A single-ended sense amplifier circuit of the invention comprises first and second MOS transistors and first and second precharge circuits. The first MOS transistor drives the bit line to a predetermined voltage and switches connection between the bit line and a sense node and the second MOS transistor whose gate is connected to the sense node amplifies the signal via the first MOS transistor. The first precharge circuit precharges the bit line to a first potential and the second precharge circuit precharges the sense node to a second potential. Before sensing operation, the bit line is driven to the predetermined voltage when the above gate voltage is controlled to decrease. The predetermined voltage is appropriately set so that a required voltage difference at the sense node between high and low levels can be obtained near a changing point between charge transfer/distributing modes.

Abstract translation: 本发明的单端读出放大器电路包括第一和第二MOS晶体管以及第一和第二预充电电路。 第一MOS晶体管将位线驱动到预定电压并且切换位线和感测节点之间的连接，并且栅极连接到感测节点的第二MOS晶体管经由第一MOS晶体管放大信号。 第一预充电电路将位线预充电到第一电位，而第二预充电电路将感测节点预充电到第二电位。 在感测操作之前，当控制上述栅极电压降低时，位线被驱动到预定电压。 适当地设定预定电压，使得可以在电荷转移/分配模式之间的变化点附近获得在高电平和低电平之间的感测节点处的所需电压差。