公开(公告)号：US08656338B2

公开(公告)日：2014-02-18

申请号：US13751811

申请日：2013-01-28

Applicant: Empire Technology Development LLC

Inventor： Farinaz Koushanfar ,  Miodrag Potkonjak

IPC: G06F17/50

CPC classification number: G06F17/50 ,  G06F17/5054 ,  G06F2217/16

Abstract: Technologies are generally described for hardware synthesis using thermally aware scheduling and binding. Multiple versions of a hardware design may be generated, each having variations of schedule and binding results. The scheduling and binding may be performed such that thermal profiles of the multiple versions have thermal peaks that are distant between the versions. The increased physical distance between the thermal peaks of the versions can give the versions unique thermal characteristics. A schedule of rotation between the multiple versions of the design may be constructed such that the thermal profile of the integrated circuit balances out during operation. A linear programming framework may be used to analyze the multiple designs and construct a thermally aware rotation scheduling and binding. For example, the K most efficient versions may be selected and then durations for operating each version within a rotation may be determined.

Abstract translation: 通常使用热感知调度和绑定来描述用于硬件合成的技术。 可以产生多个版本的硬件设计，每个版本具有日程表和绑定结果的变化。 可以执行调度和绑定，使得多个版本的热分布具有在这些版本之间较远的热峰。 这些版本的热峰之间物理距离的增加可以赋予版本独特的热特性。 可以构造设计的多个版本之间的旋转时间表，使得集成电路的热分布在操作期间平衡。 可以使用线性规划框架来分析多个设计并构建热感知旋转调度和绑定。 例如，可以选择K个最有效的版本，然后可以确定在旋转期间操作每个版本的持续时间。

公开(公告)号：US08620982B2

公开(公告)日：2013-12-31

申请号：US13855421

申请日：2013-04-02

Applicant: Empire Technology Development, LLC

Inventor： Miodrag Potkonjak ,  Farinaz Koushanfar

IPC: G06F7/38 ,  G06F7/00

CPC classification number: G01R19/25 ,  G01R31/2851 ,  G06F15/00 ,  G06F21/73

Abstract: Techniques are generally described for generating an identification number for an integrated circuit (IC). In some examples, methods for generating an identification of an IC may comprise selecting circuit elements of the IC, evaluating measurements of an attribute of the IC for the selected circuit elements, wherein individual measurements are associated with corresponding input vectors previously applied to the IC, solving a plurality of equations formulated based at least in part on the measurements taken of the attribute of the IC for the selected circuit elements to determine scaling factors for the selected circuit elements, and transforming the determined scaling factors for the selected circuit elements to generate an identification number of the IC. Additional variants and embodiments may also be disclosed.

Abstract translation: 通常描述用于产生集成电路（IC）的识别号码的技术。 在一些示例中，用于产生IC的标识的方法可以包括：选择IC的电路元件，评估用于所选择的电路元件的IC的属性的测量，其中各个测量与先前应用于IC的相应输入矢量相关联， 解决至少部分地基于针对所选择的电路元件的IC的属性的测量来确定所选择的电路元件的缩放因子并且变换所选择的电路元件的确定的缩放因子以产生 IC的识别号码。 还可以公开附加的变型和实施例。

公开(公告)号：US20140088892A1

公开(公告)日：2014-03-27

申请号：US14095252

申请日：2013-12-03

Applicant: EMPIRE TECHNOLOGY DEVELOPMENT, LLC

Inventor： Miodrag Potkonjak ,  Farinaz Koushanfar

IPC: G01R19/25

CPC classification number: G01R19/25 ,  G01R31/2851 ,  G06F15/00 ,  G06F21/73

Abstract: Techniques are generally described for generating an identification number for an integrated circuit (IC). In some examples, methods for generating an identification for an IC may comprise selecting circuit elements of the IC, evaluating measurements of an attribute of the IC for the selected circuit elements, wherein individual measurements are associated with corresponding input vectors previously applied to the IC, solving a plurality of equations formulated based at least in part on the measurements taken of the attribute of the IC for the selected circuit elements to determine scaling factors for the selected circuit elements, and transforming the determined scaling factors for the selected circuit elements to generate an identification number of the IC. Additional variants and embodiments may also be disclosed.

Abstract translation: 通常描述用于产生集成电路（IC）的识别号码的技术。 在一些示例中，用于产生IC的识别的方法可以包括选择IC的电路元件，评估用于所选择的电路元件的IC的属性的测量，其中各个测量与先前应用于IC的相应输入矢量相关联， 解决至少部分地基于针对所选择的电路元件的IC的属性的测量来确定所选择的电路元件的缩放因子并且变换所选择的电路元件的确定的缩放因子以产生 IC的识别号码。 还可以公开附加的变型和实施例。

公开(公告)号：US08788559B2

公开(公告)日：2014-07-22

申请号：US14095252

申请日：2013-12-03

Applicant: Empire Technology Development, LLC

Inventor： Miodrag Potkonjak ,  Farinaz Koushanfar

IPC: G06F17/12 ,  G06F17/11

CPC classification number: G01R19/25 ,  G01R31/2851 ,  G06F15/00 ,  G06F21/73

Abstract: Techniques are generally described for generating an identification number for an integrated circuit (IC). In some examples, methods for generating an identification for an IC may comprise selecting circuit elements of the IC, evaluating measurements of an attribute of the IC for the selected circuit elements, wherein individual measurements are associated with corresponding input vectors previously applied to the IC, solving a plurality of equations formulated based at least in part on the measurements taken of the attribute of the IC for the selected circuit elements to determine scaling factors for the selected circuit elements, and transforming the determined scaling factors for the selected circuit elements to generate an identification number of the IC. Additional variants and embodiments may also be disclosed.

Abstract translation: 通常描述用于产生集成电路（IC）的识别号码的技术。 在一些示例中，用于产生IC的识别的方法可以包括选择IC的电路元件，评估用于所选择的电路元件的IC的属性的测量，其中各个测量与先前应用于IC的相应输入矢量相关联， 解决至少部分地基于针对所选择的电路元件的IC的属性的测量来确定所选择的电路元件的缩放因子并且变换所选择的电路元件的确定的缩放因子以产生 IC的识别号码。 还可以公开附加的变型和实施例。

公开(公告)号：US20130145335A1

公开(公告)日：2013-06-06

申请号：US13751811

申请日：2013-01-28

Applicant: EMPIRE TECHNOLOGY DEVELOPMENT LLC

Inventor： Farinaz Koushanfar ,  Miodrag Potkonjak

IPC: G06F17/50

CPC classification number: G06F17/50 ,  G06F17/5054 ,  G06F2217/16

Abstract: Technologies are generally described for hardware synthesis using thermally aware scheduling and binding. Multiple versions of a hardware design may be generated, each having variations of schedule and binding results. The scheduling and binding may be performed such that thermal profiles of the multiple versions have thermal peaks that are distant between the versions. The increased physical distance between the thermal peaks of the versions can give the versions unique thermal characteristics. A schedule of rotation between the multiple versions of the design may be constructed such that the thermal profile of the integrated circuit balances out during operation. A linear programming framework may be used to analyze the multiple designs and construct a thermally aware rotation scheduling and binding. For example, the K most efficient versions may be selected and then durations for operating each version within a rotation may be determined.

Abstract translation: 通常使用热感知调度和绑定来描述用于硬件合成的技术。 可以生成多个版本的硬件设计，每个版本具有日程表和绑定结果的变化。 可以执行调度和绑定，使得多个版本的热分布具有在这些版本之间较远的热峰。 这些版本的热峰之间物理距离的增加可以赋予版本独特的热特性。 可以构造设计的多个版本之间的旋转时间表，使得集成电路的热分布在操作期间平衡。 可以使用线性规划框架来分析多个设计并构建热感知旋转调度和绑定。 例如，可以选择K个最有效的版本，然后可以确定在旋转期间操作每个版本的持续时间。