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    Interleaver Interface For A Software-Defined Radio System
    3.
    发明申请
    Interleaver Interface For A Software-Defined Radio System 失效
    用于软件定义无线电系统的交织器接口

    公开(公告)号：US20080002657A1

    公开(公告)日：2008-01-03

    申请号：US11750742

    申请日：2007-05-18

    申请人： Eran Pisek ,  Thomas Henige

    发明人： Eran Pisek ,  Thomas Henige

    IPC分类号： H04B7/216

    CPC分类号： H04L1/0055 ,  H03M13/27 ,  H03M13/2957 ,  H03M13/3905 ,  H03M13/6519 ,  H04L1/0071

    摘要： A software-defined radio (SDR) system that operates under a plurality of wireless communication standards. The SDR system comprises a reconfigurable maximum aposteriori probability (MAP) decoder capable of being configured under software control to decode a received data block according to a select wireless communication standard and a reconfigurable interleaver associated with the reconfigurable MAP decoder. The reconfigurable interleaver comprises a reconfigurable interleaver core circuitry capable of being configured under software control to operate according to the selected wireless communication standard and a unified interleaver interface for coupling a defined set of control and bus signals from the reconfigurable MAP decoder to the reconfigurable interleaver core circuitry.

    摘要翻译： 一种在多种无线通信标准下工作的软件定义无线电（SDR）系统。 SDR系统包括可配置在软件控制下的可重配置最大后验概率（MAP）解码器，以根据选择无线通信标准对接收到的数据块进行解码，以及与可重新配置的MAP解码器相关联的可重配置交织器。 可重配置交织器包括能够被配置在软件控制下以根据所选择的无线通信标准进行操作的可重配置交织器核心电路和统一的交织器接口，用于将定义的一组控制和总线信号从可重新配置的MAP解码器耦合到可重配置交织器核心 电路。

    System and method for trellis-based decoding
    4.
    发明申请
    System and method for trellis-based decoding 审中-公开
    用于网格解码的系统和方法

    公开(公告)号：US20060206697A1

    公开(公告)日：2006-09-14

    申请号：US11317268

    申请日：2005-12-23

    申请人： Eran Pisek ,  Thomas Henige

    发明人： Eran Pisek ,  Thomas Henige

    IPC分类号： G06F7/00

    CPC分类号： H03M13/3905 ,  H03M13/23 ,  H03M13/235 ,  H03M13/3776

    摘要： A decoder comprising a demodulator operable to receive a plurality of encoded data bits and generate a demodulated output, a channel decoder coupled to the demodulator operable to receive the demodulated output and generate decoded data bits, an encoder coupled to the channel decoder operable to receive the decoded data bits and re-encode the decoded data bits and generate re-encoded data bits, a comparator coupled to the demodulator and the encoder and operable to compare the demodulated output and the re-encoded data bits and generate an error rate, and wherein the error rate from the comparator is used to modify an operating parameter of the channel decoder.

    摘要翻译： 一种解码器，包括可操作以接收多个编码数据位并产生解调输出的解调器，耦合到解调器的信道解码器，可操作以接收经解调的输出并产生解码数据位;耦合到信道解码器的编码器，可操作以接收 解码的数据比特并重新编码解码的数据比特并产生重新编码的数据比特，比较器耦合到解调器和编码器，并可操作以比较解调的输出和重新编码的数据比特并产生错误率，其中 来自比较器的错误率用于修改信道解码器的操作参数。