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公开(公告)号：US06869878B1
公开(公告)日：2005-03-22
申请号：US10367406
申请日：2003-02-14
IPC分类号： H01L21/44 , H01L21/4763 , H01L21/768
CPC分类号： H01L21/76849 , H01L21/76807 , H01L21/76885
摘要： The reliability and performance of planarized metallization patterns in an electrical device, for example copper, inlaid in the surface of a layer of dielectric material overlying a semiconductor wafer substrate, are enhanced by a method for reliably depositing a barrier layer selective to the metallization patterns. The method comprises forming a sacrificial dielectric layer above a substrate. Metallization patterns are formed in the sacrificial dielectric layer. The barrier layer is selectively deposited on the metallization patterns. Portions of the barrier material undesirably deposited on the sacrificial dielectric layer are removed by removing the sacrificial dielectric layer, thus preventing bridging of adjacent metallization features by the barrier layer portions. An interlevel dielectric layer is then formed in place of the sacrificial dielectric layer. The selectively deposited barrier layer advantageously reduces parasitic capacitance between metallization features in comparison to a conventional blanket-deposited silicon nitride barrier layer.
摘要翻译： 通过用于可靠地沉积对金属化图案有选择性的阻挡层的方法，增强了嵌入在覆盖在半导体晶片衬底上的介电材料层的表面中的电子器件（例如铜）中的平面化金属化图案的可靠性和性能。 该方法包括在衬底上形成牺牲介电层。 在牺牲电介质层中形成金属化图案。 阻挡层选择性地沉积在金属化图案上。 通过去除牺牲介电层来去除不期望地沉积在牺牲介电层上的阻挡材料的部分，从而防止相邻金属化特征由阻挡层部分桥接。 然后形成层间电介质层代替牺牲电介质层。 与常规的覆盖层沉积的氮化硅阻挡层相比，选择性沉积的势垒层有利地减小了金属化特征之间的寄生电容。
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公开(公告)号：US06727592B1
公开(公告)日：2004-04-27
申请号：US10079515
申请日：2002-02-22
IPC分类号： H01L2348
CPC分类号： H01L21/76843 , H01L21/76846 , H01L21/76868 , H01L21/76871 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A Cu interconnect, e.g.; a dual damascene structure, is formed with improved electromigration resistance and increased via chain yield by depositing a barrier layer in an opening by CVD, depositing a flash layer of &agr;-Ta by PVD, at a thickness less than 30 Å, on the bottom of the barrier layer, depositing a seedlayer and then filling the opening with Cu. Embodiments include depositing a thin &agr;-Ta layer, as at a thickness less than 10 Å, and/or as discontinuous regions of clusters of atoms on sides of the opening.
摘要翻译： Cu互连，例如 通过在开口中沉积阻挡层通过CVD沉积形成具有改善的电迁移阻力并通过链产量增加的双镶嵌结构，通过PVD沉积α-Ta的闪光层，厚度小于30埃 阻挡层，沉积种子层，然后用Cu填充开口。 实施方案包括沉积厚度小于的薄的α-Ta层和/或沉积在开口侧面上的原子簇的不连续区域。
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公开(公告)号：US06525428B1
公开(公告)日：2003-02-25
申请号：US10183458
申请日：2002-06-28
IPC分类号： H01L2348
CPC分类号： H01L21/76832 , H01L21/76807 , H01L23/5222 , H01L23/53228 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , Y10S438/931 , H01L2924/00
摘要： Improved etch selectivity, barrier metal wetting and reduced interconnect capacitance are achieved by implementing damascene processing employing a graded middle etch stop layer comprising a first silicon carbide layer, a silicon-rich layer on the first silicon carbide, and a second silicon carbide layer on the silicon-rich layer. Embodiments include sequentially depositing a porous low-k dielectric layer over a lower capped Cu line, depositing the graded middle-etch stop layer, depositing a porous low-k dielectric layer on the graded middle-etch stop layer, forming a dual damascene opening exposing the silicon-rich surface at the bottom of the trench opening, depositing a seed layer, depositing a barrier middle layer, such as Ta or a Ta/TaN composite, and filling the opening with Cu.
摘要翻译： 改进的蚀刻选择性，阻挡金属润湿和降低的互连电容通过实施使用包括第一碳化硅层，第一碳化硅上的富硅层和第二碳化硅层上的第二碳化硅层的分级中间蚀刻停止层的镶嵌加工来实现 富硅层。 实施例包括在下部封装的Cu线上顺序沉积多孔低k电介质层，沉积渐变的中间蚀刻停止层，在分级中间蚀刻停止层上沉积多孔低k电介质层，形成双镶嵌开口露出 在沟槽开口的底部的富硅表面，沉积种子层，沉积阻挡中间层，如Ta或Ta / TaN复合材料，并用Cu填充开口。
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