公开(公告)号：US20190164855A1

公开(公告)日：2019-05-30

申请号：US15749444

申请日：2018-01-02

申请人： Wuhan China Star Optoelectronics Technology Co., Ltd.

发明人： Guanghui HONG ,  Qiang GONG

IPC分类号： H01L21/66 ,  H01L27/12

CPC分类号： H01L22/22 ,  G02F1/1309 ,  H01L21/485 ,  H01L21/76868 ,  H01L21/76894 ,  H01L22/14 ,  H01L27/124

摘要： The present invention provides an array substrate and an repairing method thereof, wherein the array substrate includes adjacent two level GOA unit circuits, wherein an output terminal of a Nth level GOA unit circuit is connected to a Nth level gate line, an output terminal of a N+1th level GOA unit circuit is connected to a N+1th level gate line; and a repairing structure disposed between the Nth level gate line and the N+1th level gate line, the repairing structure configured to turn on the Nth level gate line and the N+1th level gate line by melting when the Nth level GOA unit circuit or the N+1th level GOA unit circuit damaged. A repairing structure is added between two adjacent gate lines, when a certain GOA unit circuit is damaged, the repairing structure is melted by a laser to make the adjacent two gate lines communicate with each other.

公开(公告)号：US20180327893A1

公开(公告)日：2018-11-15

申请号：US16033166

申请日：2018-07-11

申请人： Applied Materials, Inc.

发明人： Peijun DING ,  Rong TAO ,  Zheng XU ,  Daniel C. LUBBEN ,  Suraj RENGARAJAN ,  Michael A. MILLER ,  Arvind SUNDARRAJAN ,  Xianmin TANG ,  John C. FORSTER ,  Jianming FU ,  Roderick C. MOSELY ,  Fusen CHEN ,  Praburam GOPALRAJA

IPC分类号： C23C14/04 ,  C23C14/56 ,  C23C14/35 ,  H01J37/32 ,  H01J37/34 ,  H01L21/285 ,  H01L21/768 ,  C23C14/34

CPC分类号： C23C14/046 ,  C23C14/345 ,  C23C14/3457 ,  C23C14/35 ,  C23C14/358 ,  C23C14/564 ,  C23C14/568 ,  H01J37/321 ,  H01J37/3402 ,  H01J37/3408 ,  H01J37/3441 ,  H01J2237/3327 ,  H01L21/2855 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76868 ,  H01L21/76871 ,  H01L21/76873 ,  H01L21/76876 ,  H01L21/76877 ,  H01L2221/1089

摘要： A magnetron sputter reactor for sputtering deposition materials such as tantalum, tantalum nitride and copper, for example and its method of use, in which self-ionized plasma (SIP) sputtering and inductively coupled plasma (ICP) sputtering are promoted, either together or alternately, in the same or different chambers. Also, bottom coverage may be thinned or eliminated by ICP resputtering in one chamber and SIP in another. SIP is promoted by a small magnetron having poles of unequal magnetic strength and a high power applied to the target during sputtering. ICP is provided by one or more RF coils which inductively couple RF energy into a plasma. The combined SIP-ICP layers can act as a liner or barrier or seed or nucleation layer for hole. In addition, an RF coil may be sputtered to provide protective material during ICP resputtering. In another chamber an array of auxiliary magnets positioned along sidewalls of a magnetron sputter reactor on a side towards the wafer from the target. The magnetron preferably is a small, strong one having a stronger outer pole of a first magnetic polarity surrounding a weaker outer pole of a second magnetic polarity and rotates about the central axis of the chamber. The auxiliary magnets preferably have the first magnetic polarity to draw the unbalanced magnetic field component toward wafer. The auxiliary magnets may be either permanent magnets or electromagnets.

公开(公告)号：US10047430B2

公开(公告)日：2018-08-14

申请号：US14205260

申请日：2014-03-11

申请人： Applied Materials, Inc.

发明人： Peijun Ding ,  Rong Tao ,  Zheng Xu ,  Daniel C. Lubben ,  Suraj Rengarajan ,  Michael A. Miller ,  Arvind Sundarrajan ,  Xianmin Tang ,  John C. Forster ,  Jianming Fu ,  Roderick C. Mosely ,  Fusen Chen ,  Praburam Gopalraja

IPC分类号： C23C14/34 ,  H01J37/34 ,  C23C14/04 ,  C23C14/35 ,  C23C14/56 ,  H01J37/32 ,  H01L21/285 ,  H01L21/768

CPC分类号： C23C14/046 ,  C23C14/345 ,  C23C14/3457 ,  C23C14/35 ,  C23C14/358 ,  C23C14/564 ,  C23C14/568 ,  H01J37/321 ,  H01J37/3402 ,  H01J37/3408 ,  H01J37/3441 ,  H01J2237/3327 ,  H01L21/2855 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76868 ,  H01L21/76871 ,  H01L21/76873 ,  H01L21/76876 ,  H01L21/76877 ,  H01L2221/1089

摘要： A magnetron sputter reactor for sputtering deposition materials such as tantalum, tantalum nitride and copper, for example, and its method of use, in which self-ionized plasma (SIP) sputtering and inductively coupled plasma (ICP) sputtering are promoted, either together or alternately, in the same or different chambers. Also, bottom coverage may be thinned or eliminated by ICP resputtering in one chamber and SIP in another. SIP is promoted by a small magnetron having poles of unequal magnetic strength and a high power applied to the target during sputtering. ICP is provided by one or more RF coils which inductively couple RF energy into a plasma. The combined SIP-ICP layers can act as a liner or barrier or seed or nucleation layer for hole. In addition, an RF coil may be sputtered to provide protective material during ICP resputtering. In another chamber an array of auxiliary magnets positioned along sidewalls of a magnetron sputter reactor on a side towards the wafer from the target. The magnetron preferably is a small, strong one having a stronger outer pole of a first magnetic polarity surrounding a weaker outer pole of a second magnetic polarity and rotates about the central axis of the chamber. The auxiliary magnets preferably have the first magnetic polarity to draw the unbalanced magnetic field component toward the wafer. The auxiliary magnets may be either permanent magnets or electromagnets.

公开(公告)号：US10037940B2

公开(公告)日：2018-07-31

申请号：US15623228

申请日：2017-06-14

申请人： Tessera, Inc.

发明人： Cyprian Emeka Uzoh ,  Belgacem Haba ,  Craig Mitchell

IPC分类号： H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522 ,  H01L23/48 ,  H01L21/321 ,  H01L21/288

CPC分类号： H01L23/528 ,  H01L21/2885 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76868 ,  H01L21/76873 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53238 ,  H01L24/13 ,  H01L24/14 ,  H01L2221/1094 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/14181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/05552

摘要： Methods and apparatus for forming a semiconductor device are provided which may include any number of features. One feature is a method of forming an interconnect structure that results in the interconnect structure having a top surface and portions of the side walls of the interconnect structure covered in a dissimilar material. In some embodiments, the dissimilar material can be a conductive material or a nano-alloy. The interconnect structure can be formed by removing a portion of the interconnect structure, and covering the interconnect structure with the dissimilar material. The interconnect structure can comprise a damascene structure, such as a single or dual damascene structure, or alternatively, can comprise a silicon-through via (TSV) structure.

公开(公告)号：US20170263456A1

公开(公告)日：2017-09-14

申请号：US15606601

申请日：2017-05-26

申请人： Micron Technology, Inc.

发明人： Gurtej S. Sandhu

IPC分类号： H01L21/033 ,  B81C1/00 ,  H01L21/308 ,  H01L21/768

CPC分类号： H01L21/0338 ,  B81C1/00031 ,  B81C2201/0149 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/76868 ,  H01L2221/1094 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a nanostructure comprises forming self-assembled nucleic acids on at least a portion of a substrate. The method further comprises contacting the self-assembled nucleic acids on the at least a portion of a substrate with a solution comprising at least one repair enzyme to repair defects in the self-assembled nucleic acids. The method may comprise repeating the repair of defects in the self-assembled nucleic acids on the at least a portion of a substrate until a desired, reduced threshold level of defect density is achieved. A semiconductor structure comprises a pattern of self-assembled nucleic acids defining a template having at least one aperture therethrough. At least one of the apertures has a dimension of less than about 50 nm.

公开(公告)号：US09711401B2

公开(公告)日：2017-07-18

申请号：US15195641

申请日：2016-06-28

申请人： Tessera, Inc.

发明人： Cyprian Emeka Uzoh ,  Belgacem Haba ,  Craig Mitchell

IPC分类号： H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L23/00

CPC分类号： H01L23/528 ,  H01L21/2885 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76868 ,  H01L21/76873 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53238 ,  H01L24/13 ,  H01L24/14 ,  H01L2221/1094 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/14181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/05552

摘要： Methods and apparatus for forming a semiconductor device are provided which may include any number of features. One feature is a method of forming an interconnect structure that results in the interconnect structure having a top surface and portions of the side walls of the interconnect structure covered in a dissimilar material. In some embodiments, the dissimilar material can be a conductive material or a nano-alloy. The interconnect structure can be formed by removing a portion of the interconnect structure, and covering the interconnect structure with the dissimilar material. The interconnect structure can comprise a damascene structure, such as a single or dual damascene structure, or alternatively, can comprise a silicon-through via (TSV) structure.

公开(公告)号：US20160307798A1

公开(公告)日：2016-10-20

申请号：US15195641

申请日：2016-06-28

申请人： Invensas Corporation

发明人： Cyprian Emeka UZOH ,  Belgacem HABA ,  Craig MITCHELL

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L23/48

CPC分类号： H01L23/528 ,  H01L21/2885 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76868 ,  H01L21/76873 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53238 ,  H01L24/13 ,  H01L24/14 ,  H01L2221/1094 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/14181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/05552

摘要： Methods and apparatus for forming a semiconductor device are provided which may include any number of features. One feature is a method of forming an interconnect structure that results in the interconnect structure having a top surface and portions of the side walls of the interconnect structure covered in a dissimilar material. In some embodiments, the dissimilar material can be a conductive material or a nano-alloy. The interconnect structure can be formed by removing a portion of the interconnect structure, and covering the interconnect structure with the dissimilar material. The interconnect structure can comprise a damascene structure, such as a single or dual damascene structure, or alternatively, can comprise a silicon-through via (TSV) structure.

摘要翻译： 提供了用于形成半导体器件的方法和装置，其可以包括任何数量的特征。 一个特征是形成互连结构的方法，其导致互连结构具有覆盖在不同材料中的互连结构的顶表面和侧壁的部分。 在一些实施例中，异种材料可以是导电材料或纳米合金。 互连结构可以通过去除互连结构的一部分并且用不同材料覆盖互连结构来形成。 互连结构可以包括镶嵌结构，例如单镶嵌结构或双镶嵌结构，或者可以包括硅通孔（TSV）结构。

公开(公告)号：US09275871B2

公开(公告)日：2016-03-01

申请号：US14151635

申请日：2014-01-09

申请人： Micron Technology, Inc.

发明人： Gurtej S. Sandhu

IPC分类号： H01L51/40 ,  G01N15/06 ,  G01N33/00 ,  G01N33/48 ,  H01L21/308

CPC分类号： H01L21/0338 ,  B81C1/00031 ,  B81C2201/0149 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/76868 ,  H01L2221/1094 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming nanostructure comprises forming self-assembled nucleic acids on at least a portion of a substrate. The method further comprises contacting the self-assembled nucleic acids on the at least a portion of a substrate with a solution comprising at least one repair enzyme to repair defects in the self-assembled nucleic acids. The method may comprise repeating the repair of defects in the self-assembled nucleic acids on the at least a portion of a substrate until a desired, reduced threshold level of defect density is achieved. A semiconductor structure comprises a pattern of self-assembled nucleic acids defining a template having at least one aperture therethrough. At least one of the apertures has a dimension of less than about 50 nm.

摘要翻译： 形成纳米结构的方法包括在基底的至少一部分上形成自组装核酸。 该方法还包括使底物的至少一部分上的自组装核酸与包含至少一种修复酶的溶液接触，以修复自组装核酸中的缺陷。 该方法可以包括重复在衬底的至少一部分上的自组装核酸中的缺陷的修复，直到达到期望的降低的阈值水平的缺陷密度。 半导体结构包括限定模板的自组装核酸的图案，其具有穿过其中的至少一个孔。 孔中的至少一个具有小于约50nm的尺寸。

公开(公告)号：US20150194316A1

公开(公告)日：2015-07-09

申请号：US14151635

申请日：2014-01-09

申请人： Micron Technology, Inc.

发明人： Gurtej S. Sandhu

IPC分类号： H01L21/308 ,  H01L23/00

CPC分类号： H01L21/0338 ,  B81C1/00031 ,  B81C2201/0149 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/76868 ,  H01L2221/1094 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming nanostructure comprises forming self-assembled nucleic acids on at least a portion of a substrate. The method further comprises contacting the self-assembled nucleic acids on the at least a portion of a substrate with a solution comprising at least one repair enzyme to repair defects in the self-assembled nucleic acids. The method may comprise repeating the repair of defects in the self-assembled nucleic acids on the at least a portion of a substrate until a desired, reduced threshold level of defect density is achieved. A semiconductor structure comprises a pattern of self-assembled nucleic acids defining a template having at least one aperture therethrough. At least one of the apertures has a dimension of less than about 50 nm.

摘要翻译： 形成纳米结构的方法包括在基底的至少一部分上形成自组装核酸。 该方法还包括使底物的至少一部分上的自组装核酸与包含至少一种修复酶的溶液接触，以修复自组装核酸中的缺陷。 该方法可以包括重复在衬底的至少一部分上的自组装核酸中的缺陷的修复，直到达到期望的降低的阈值水平的缺陷密度。 半导体结构包括限定模板的自组装核酸的图案，其具有穿过其中的至少一个孔。 孔中的至少一个具有小于约50nm的尺寸。

公开(公告)号：US08993434B2

公开(公告)日：2015-03-31

申请号：US13226612

申请日：2011-09-07

申请人： Jick M. Yu ,  Rong Tao ,  Xinyu Fu

发明人： Jick M. Yu ,  Rong Tao ,  Xinyu Fu

IPC分类号： H01L21/4763 ,  H01L21/285 ,  H01L21/768

CPC分类号： H01L21/2855 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76868 ,  H01L21/76873 ,  H01L21/76879 ,  H01L2221/1089

摘要： Methods for forming layers on a substrate having one or more features formed therein are provided herein. In some embodiments, a method for forming layers on a substrate having one or more features formed therein may include depositing a seed layer within the one or more features; and etching the seed layer to remove at least a portion of the seed layer proximate an opening of the feature such that the seed layer comprises a first thickness disposed on a lower portion of a sidewall of the feature proximate a bottom of the feature and a second thickness disposed on an upper portion of the sidewall proximate the opening of the feature and wherein the first thickness is greater than the second thickness.

摘要翻译： 本文提供了在其上形成有一个或多个特征的基底上形成层的方法。 在一些实施例中，用于在其上形成有一个或多个特征的衬底上形成层的方法可包括在一个或多个特征内沉积晶种层; 并且蚀刻种子层以去除邻近特征的开口的种子层的至少一部分，使得种子层包括设置在靠近特征的底部的特征的侧壁的下部的第一厚度，以及第二 厚度设置在靠近特征开口的侧壁的上部，并且其中第一厚度大于第二厚度。