公开(公告)号：US20130031523A1

公开(公告)日：2013-01-31

申请号：US13190083

申请日：2011-07-25

申请人： Eric A. FOREMAN ,  Peter A. HABITZ ,  David J. HATHAWAY ,  Jeffrey G. Hemmett ,  Natesan VENKATESWARAN ,  Chandramouli VISWESWARIAH ,  Vladimir ZOLOTOV

发明人： Eric A. FOREMAN ,  Peter A. HABITZ ,  David J. HATHAWAY ,  Jeffrey G. Hemmett ,  Natesan VENKATESWARAN ,  Chandramouli VISWESWARIAH ,  Vladimir ZOLOTOV

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： G06F17/5031 ,  G06F17/5081

摘要： Systems and methods for accommodating correlated parameters in SSTA are provided. The method includes determining a correlation between at least two parameters. The method further includes calculating a new parameter or a new parameter set based on the correlation between the at least two parameters. The method further includes performing the SSTA such that the new parameter or the new parameter set is propagated into the SSTA. The method further includes projecting slack using the correlation between the at least two parameters and using a processor.

公开(公告)号：US20130145333A1

公开(公告)日：2013-06-06

申请号：US13311832

申请日：2011-12-06

申请人： Nathan BUCK ,  Brian DREIBELBIS ,  John P. DUBUQUE ,  Eric A. FOREMAN ,  James C. GREGERSON ,  Peter A. HABITZ ,  Jeffrey G. HEMMETT ,  Debjit SINHA ,  Natesan VENKATESWARAN ,  Chandramouli VISWESWARIAH ,  Michael H. WOOD ,  Vladimir ZOLOTOV

发明人： Nathan BUCK ,  Brian DREIBELBIS ,  John P. DUBUQUE ,  Eric A. FOREMAN ,  James C. GREGERSON ,  Peter A. HABITZ ,  Jeffrey G. HEMMETT ,  Debjit SINHA ,  Natesan VENKATESWARAN ,  Chandramouli VISWESWARIAH ,  Michael H. WOOD ,  Vladimir ZOLOTOV

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F2217/10 ,  G06F2217/62

摘要： Systems and methods for statistical clock cycle computation and closing timing of an integrated circuit design to a maximum clock cycle or period. The method includes loading a design and timing model for at least one circuit path of an integrated circuit or a region of the integrated circuit into a computing device. The method further includes performing a statistical static timing analysis (SSTA) of the at least one circuit path using the loaded design and timing model to obtain slack canonical data. The method further includes calculating a maximum circuit clock cycle for the integrated circuit or the specified region of the integrated circuit in linear canonical form based upon the slack canonical data obtained from the SSTA.

摘要翻译： 将集成电路设计的统计时钟周期计算和闭合时序的系统和方法设计到最大时钟周期或周期。 该方法包括将用于集成电路或集成电路的区域的至少一个电路路径的设计和定时模型加载到计算设备中。 该方法还包括使用加载的设计和定时模型来执行至少一个电路路径的统计静态时序分析（SSTA），以获得松散的规范数据。 该方法还包括基于从SSTA获得的松弛规范数据，以线性规范形式计算集成电路或集成电路的指定区域的最大电路时钟周期。

公开(公告)号：US20080313590A1

公开(公告)日：2008-12-18

申请号：US12183549

申请日：2008-07-31

申请人： Eric A. FOREMAN ,  Peter A. Habitz ,  David J. Hathaway ,  Jerry D. Hayes ,  Anthony D. Polson

发明人： Eric A. FOREMAN ,  Peter A. Habitz ,  David J. Hathaway ,  Jerry D. Hayes ,  Anthony D. Polson

IPC分类号： G06F17/50

CPC分类号： G01R31/3016

摘要： Methods for analyzing the timing in integrated circuits and for reducing the pessimism in timing slack calculations in static timing analysis (STA). The methods involve grouping and canceling the delay contributions of elements having similar delays in early and late circuit paths. An adjusted timing slack is calculated using the delay contributions of elements having dissimilar delays. In some embodiments, the delay contributions of elements having dissimilar delays are root sum squared. Embodiments of the invention provide methods for reducing the pessimism due to both cell-based and wire-dependent delays. The delays considered in embodiments of the invention may include delays due to the location of elements in a path.

摘要翻译： 用于分析集成电路中的定时并减少静态时序分析（STA）中定时松弛计算中的悲观情况的方法。 该方法涉及分组和消除在早期和晚期电路路径中具有类似延迟的元件的延迟贡献。 使用具有不同延迟的元件的延迟贡献来计算调整的定时松弛。 在一些实施例中，具有不同延迟的元件的延迟贡献是根和平方。 本发明的实施例提供了用于减少由于基于单元和线依赖的延迟引起的悲观的方法。 在本发明的实施例中考虑的延迟可以包括由于路径中的元件的位置而导致的延迟。