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    Adaptive power control using timing canonicals
    2.
    发明授权
    Adaptive power control using timing canonicals 有权
    使用定时规范的自适应功率控制

    公开(公告)号：US09157956B2

    公开(公告)日：2015-10-13

    申请号：US13614564

    申请日：2012-09-13

    申请人： Jeanne P. Bickford ,  Eric A. Foreman ,  Peter A. Habitz ,  Jeffrey G. Hemmett ,  Clarence R. Ogilvie ,  Tad J. Wilder ,  Vladimir Zolotov

    发明人： Jeanne P. Bickford ,  Eric A. Foreman ,  Peter A. Habitz ,  Jeffrey G. Hemmett ,  Clarence R. Ogilvie ,  Tad J. Wilder ,  Vladimir Zolotov

    IPC分类号： G06F17/50 ,  G01R31/317 ,  G01R31/30

    CPC分类号： G01R31/31718 ,  G01R31/3008

    摘要： A plurality of digital circuits are manufactured from an identical circuit design. A power controller is operatively connected to the digital circuits, and a non-transitory storage medium is operatively connected to the power controller. The digital circuits are classified into different voltage bins, and each of the voltage bins has a current leakage limit. Each of the digital circuits has been previously tested to operate within a corresponding current leakage limit of a corresponding voltage bin into which each of the digital circuits has been classified. The non-transitory storage medium stores boundaries of the voltage bins as speed-binning test data. The power controller controls power-supply signals applied differently for each of the digital circuits based on which bin each of the digital circuit has been classified and the speed-binning test data.

    摘要翻译： 由相同的电路设计制造多个数字电路。 功率控制器可操作地连接到数字电路，并且非瞬时存储介质可操作地连接到功率控制器。 数字电路分为不同的电压箱，每个电压箱都有漏电极限。 已经对每个数字电路进行了测试，以在对应的电压仓的相应的电流泄漏极限内运行，每个数字电路已被分类到该对应的电压仓。 非瞬时存储介质存储电压仓的边界作为速度分组测试数据。 功率控制器控制基于每个数字电路已被分类的每个数字电路不同地施加的电源信号和速度合并测试数据。

    POWER/PERFORMANCE OPTIMIZATION THROUGH TEMPERATURE/VOLTAGE CONTROL
    3.
    发明申请
    POWER/PERFORMANCE OPTIMIZATION THROUGH TEMPERATURE/VOLTAGE CONTROL 有权
    功率/性能优化通过温度/电压控制

    公开(公告)号：US20130326459A1

    公开(公告)日：2013-12-05

    申请号：US13749851

    申请日：2013-01-25

    申请人： Jeanne P. Bickford ,  Eric A. Foreman ,  Mark W. Kuemerle ,  Susan K. Lichtensteiger

    发明人： Jeanne P. Bickford ,  Eric A. Foreman ,  Mark W. Kuemerle ,  Susan K. Lichtensteiger

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045 ,  G01R31/31721 ,  G06F17/5031

    摘要： A method of optimizing power and timing for an integrated circuit (IC) chip, identifies a plurality of valid temperature and voltage combinations that allow integrated circuit chips produced according to the integrated circuit chip design to operate within average power consumption goals and timing delay goals. Such a method selects temperature cut points from the valid temperature and voltage combinations for each of the integrated circuit chips, calculates a power consumption amount of each of the temperature cut points, and adjusts the temperature cut points based on the power consumption amount until the temperature cut points achieve the average power consumption goals. Next, this method tests each of the integrated circuit chips, and records the temperature cut points in the memory of the integrated circuit chips.

    摘要翻译： 一种优化集成电路（IC）芯片的功率和定时的方法，识别允许根据集成电路芯片设计产生的集成电路芯片在平均功耗目标和时序延迟目标内工作的多个有效的温度和电压组合。 这种方法从每个集成电路芯片的有效温度和电压组合中选择温度切割点，计算每个温度切断点的功率消耗量，并且基于功耗量调节温度切断点直到温度 切点实现了平均功耗目标。 接下来，该方法测试每个集成电路芯片，并将温度切割点记录在集成电路芯片的存储器中。

    Device history based delay variation adjustment during static timing analysis
    6.
    发明授权
    Device history based delay variation adjustment during static timing analysis 有权
    静态时序分析期间基于设备历史的延迟变化调整

    公开(公告)号：US08108816B2

    公开(公告)日：2012-01-31

    申请号：US12484293

    申请日：2009-06-15

    申请人： Eric A. Foreman ,  Peter A. Habitz ,  David J. Hathaway ,  Jeffrey G. Hemmett ,  Kerim Kalafala ,  Jeffrey P. Soreff

    发明人： Eric A. Foreman ,  Peter A. Habitz ,  David J. Hathaway ,  Jeffrey G. Hemmett ,  Kerim Kalafala ,  Jeffrey P. Soreff

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031 ,  G06F17/504 ,  G06F2217/84

    摘要： A system and method for the adjustment of history based delay variation during static timing analysis of an integrated circuit design. The method may include obtaining information through sources of variability of history based components of delay variability, and a relationship between the sources of variability and one or more bounded device histories. Then, inputting history bounds for at least one signal of the integrated circuit design, and computing and propagating history bounds through at least one first segment of the integrated circuit design to at least one signal of the integrated circuit design. Further, the method may include evaluating from at least one of the propagated history bounds, device history bounds for at least one second segment of the integrated circuit design, and based on the evaluated device history bounds, adjusting at least one of a value of the history based delay variability and propagation of timing.

    摘要翻译： 一种用于在集成电路设计的静态时序分析期间调整基于历史的延迟变化的系统和方法。 该方法可以包括通过延迟变异性的基于历史的组件的变异源获得信息，以及变异源与一个或多个有界设备历史之间的关系。 然后，为集成电路设计的至少一个信号输入历史界限，并且通过集成电路设计的至少一个第一段将集成电路设计的至少一个信号计算和传播历史界限。 此外，该方法可以包括从至少一个传播的历史界限评估集成电路设计的至少一个第二段的设备历史界限，以及基于所评估的设备历史界限，调整至少一个 基于历史的延迟变异性和时间传播。

    Methods for identifying failing timing requirements in a digital design
    7.
    发明授权
    Methods for identifying failing timing requirements in a digital design 有权
    识别数字设计中的故障定时要求的方法

    公开(公告)号：US07886246B2

    公开(公告)日：2011-02-08

    申请号：US12103845

    申请日：2008-04-16

    申请人： Nathan C. Buck ,  John P. Dubuque ,  Eric A. Foreman ,  Peter A. Habitz ,  Chandramouli Visweswariah

    发明人： Nathan C. Buck ,  John P. Dubuque ,  Eric A. Foreman ,  Peter A. Habitz ,  Chandramouli Visweswariah

    IPC分类号： G06F17/50 ,  G06F9/45

    CPC分类号： G06F17/5031

    摘要： Methods for identifying failing timing requirements in a digital design. The method includes identifying at least one timing test in the digital design that has a passing slack in a base process corner and a failing slack in a different process corner. The method further includes computing a sensitivity of the failing slack to each of a plurality of variables and comparing each sensitivity to a respective sensitivity threshold. If the sensitivity of at least one of the variables is greater than the respective sensitivity threshold, then the at least one timing test is considered to fail.

    摘要翻译： 识别数字设计中的故障定时要求的方法。 该方法包括识别数字设计中的至少一个定时测试，其在基本过程角落中具有通过松弛，并且在不同的过程角落中发生故障的松弛。 该方法还包括计算对于多个变量中的每一个的故障松弛的灵敏度，并将每个灵敏度与相应的灵敏度阈值进行比较。 如果至少一个变量的灵敏度大于相应的灵敏度阈值，则认为至少一个定时测试失败。

    METHOD AND SYSTEM FOR EVALUATING STATISTICAL SENSITIVITY CREDIT IN PATH-BASED HYBRID MULTI-CORNER STATIC TIMING ANALYSIS
    10.
    发明申请
    METHOD AND SYSTEM FOR EVALUATING STATISTICAL SENSITIVITY CREDIT IN PATH-BASED HYBRID MULTI-CORNER STATIC TIMING ANALYSIS 失效
    基于路径的混合多角度静态时序分析评估统计灵敏度信息的方法和系统

    公开(公告)号：US20080209373A1

    公开(公告)日：2008-08-28

    申请号：US11679251

    申请日：2007-02-27

    申请人： Nathan C. Buck ,  John P. Dubuque ,  Eric A. Foreman ,  Peter A. Habitz ,  Kerim Kalafala ,  Peihua Qi ,  Chandramouli Visweswariah ,  Xiaoyue Wang

    发明人： Nathan C. Buck ,  John P. Dubuque ,  Eric A. Foreman ,  Peter A. Habitz ,  Kerim Kalafala ,  Peihua Qi ,  Chandramouli Visweswariah ,  Xiaoyue Wang

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031

    摘要： Methods, systems and computer program products for analyzing a timing design of an integrated circuit are disclosed. According to an embodiment, a method for analyzing a timing design of an integrated circuit comprises: providing an initial static timing analysis of the integrated circuit; selecting a static timing test with respect to a static timing test point based on the initial static timing analysis; selecting a timing path leading to the static timing test point for the static timing test; determining an integrated slack path variability for the timing path based on a joint probability distribution of at least one statistically independent parameter; and analyzing the timing design based on the integrated slack path variability.

    摘要翻译： 公开了用于分析集成电路的定时设计的方法，系统和计算机程序产品。 根据实施例，用于分析集成电路的定时设计的方法包括：提供集成电路的初始静态时序分析; 基于初始静态时序分析，选择静态定时测试点的静态定时测试; 选择通过静态定时测试的静态定时测试点的定时路径; 基于至少一个统计学独立参数的联合概率分布来确定所述定时路径的综合松弛路径可变性; 并基于综合的松弛路径变异性分析时序设计。