公开(公告)号：US07912156B1

公开(公告)日：2011-03-22

申请号：US10820347

申请日：2004-04-07

申请人： Eric K. Hall ,  Ayyoob Abbaszadeh ,  Thomas R. Giallorenzi

发明人： Eric K. Hall ,  Ayyoob Abbaszadeh ,  Thomas R. Giallorenzi

IPC分类号： H04L27/06

CPC分类号： H04L27/20 ,  H03M13/152 ,  H03M13/2906 ,  H03M13/2936 ,  H03M13/2957 ,  H03M13/373 ,  H03M13/63 ,  H04B7/18506 ,  H04L1/0045 ,  H04L1/0065 ,  H04L1/0066

摘要： Method and apparatus are disclosed for obtaining improved performance when using Forward Error Correction (FEC) with channels experiencing block fading or burst jamming over some number of contiguous symbols. One suitable application is when the channel is periodically obstructed due to the rotation of a propeller blade, resulting in a periodic block fading channel. During operation zero symbols are inserted into the received signal stream, prior to the FEC decoder at times that are estimated or otherwise determined to correspond to periods of jamming or severe fading. The zero symbols effectively “erase” the severely degraded symbols. The zero symbols are less detrimental to the FEC decoder than the severely degraded symbols, especially when the channel interleaving/de-interleaving operations result in the zero symbols being temporarily distributed over a large block of received symbols.

摘要翻译： 公开了用于在使用经过块衰落的信道的前向纠错（FEC）或在某些数量的连续符号上的突发干扰时获得改进的性能的方法和装置。 一个合适的应用是当通道由于螺旋桨叶片的旋转而周期性地阻塞时，导致周期性的块衰落通道。 在操作期间，在被估计或以其他方式确定为对应于干扰或严重衰落的周期的时间，在FEC解码器之前，零符号被插入到接收信号流中。 零符号有效地“抹除”严重退化的符号。 特别是当信道交织/解交织操作导致零符号临时分布在大块接收到的符号上时，零符号对FEC解码器的影响比严重降级的符号更不利。

公开(公告)号：US07783936B1

公开(公告)日：2010-08-24

申请号：US11540134

申请日：2006-09-28

申请人： Eric K. Hall ,  Ayyoob Abbaszadeh ,  Richard Ertel

发明人： Eric K. Hall ,  Ayyoob Abbaszadeh ,  Richard Ertel

IPC分类号： H03M13/03 ,  G11C29/00 ,  G06F11/00

CPC分类号： G06F11/1008 ,  H03M13/2957 ,  H03M13/3972 ,  H03M13/6566

摘要： A technique for resolving access contention in a parallel turbo decoder is described. The technique includes associating a plurality of buffer memories with the subdecoders so that accesses to banks of a shared interleaver memory can be rescheduled. Accesses can be rescheduled to prevent simultaneous accesses to a single bank of the shared interleaver memory based on an interleaver pattern.

摘要翻译： 描述了用于解决并行turbo解码器中的访问争用的技术。 该技术包括将多个缓冲存储器与子解码器相关联，使得可以重新调度对共享交织器存储器的存储体的访问。 可以重新调度访问以防止基于交织器模式同时访问共享交织器存储器的单个存储体。

公开(公告)号：US07953781B1

公开(公告)日：2011-05-31

申请号：US11754922

申请日：2007-05-29

申请人： Ayyoob Abbaszadeh ,  Altaf Rahman ,  Merle Keller

发明人： Ayyoob Abbaszadeh ,  Altaf Rahman ,  Merle Keller

IPC分类号： G06F7/58

CPC分类号： G06F7/582

摘要： A system and method for parallel Pseudo-random Noise (PN) code generation is disclosed. The method includes the operation of producing a PN code sequence having a predetermined length. The PN code can be divided into L segments. At least one of the L segments can have a length less than other segments. The L segments can be distributed into an array of L digital memories. Each of the digital memories can output every Lth chip of the PN code in parallel at a selected rate. An element of the PN code can be substituted from an element substitution cache into the output of the L digital memories to compensate for segment(s) having a shorter length.

摘要翻译： 公开了一种用于并行伪随机噪声（PN）码生成的系统和方法。 该方法包括产生具有预定长度的PN码序列的操作。 PN码可以分为L段。 L段中的至少一个可以具有小于其他段的长度。 L段可以分布到L数字存储器的阵列中。 每个数字存储器可以以选定的速率并行输出PN码的每个Lth码片。 PN代码的元素可以从元素替换高速缓存代入L数字存储器的输出以补偿具有较短长度的段。

公开(公告)号：US08266493B1

公开(公告)日：2012-09-11

申请号：US11971876

申请日：2008-01-09

申请人： Ayyoob Abbaszadeh ,  Ryan Hinton

发明人： Ayyoob Abbaszadeh ,  Ryan Hinton

IPC分类号： H03M13/00 ,  H03M13/03 ,  G11C29/00 ,  H04N7/12

CPC分类号： H03M13/1137 ,  H03M13/1134 ,  H03M13/116

摘要： A technique for decoding low-density parity check codes includes performing a combined check node and variable node calculation. Decoding is initialized using channel likelihood values estimated from a received physical signal. The decoding iteratively updates the variable nodes. Performing a combined check node and variable node calculation can enable reduced memory usage and faster convergence for the decoder.

摘要翻译： 用于解码低密度奇偶校验码的技术包括执行组合校验节点和可变节点计算。 使用从接收到的物理信号估计的信道似然值来初始化解码。 解码迭代地更新变量节点。 执行组合校验节点和变量节点计算可以使解码器减少内存使用和更快的收敛。

公开(公告)号：US08065585B1

公开(公告)日：2011-11-22

申请号：US11897367

申请日：2007-08-30

申请人： Ayyoob Abbaszadeh ,  David Todd Wilstead

发明人： Ayyoob Abbaszadeh ,  David Todd Wilstead

IPC分类号： H03M13/00

CPC分类号： H03M13/2963 ,  H03M13/152 ,  H03M13/19 ,  H03M13/47 ,  H03M13/611 ,  H03M13/618 ,  H03M13/6561

摘要： A source controller provides a block of n×a information bits as n separate rows each with a information bits. A row encoder has an input coupled to an output of the source controller and includes a plurality of accumulators arranged to process m of the information bits in one clock cycle to generate row forward error correction FEC bits. At least one column encoder has an input coupled to an output of the source controller and is arranged to generate column FEC bits in parallel with the row encoder. A multiplexer is coupled to outputs of the row and column encoders and is adapted to serially output an nth row of information bits followed by the nth row FEC bits for each of the n rows, followed by additional rows of FEC bits generated by the column encoder. The terms n, m, and a are integers greater than one. Where more than one column encoder is used, there are preferably m column encoders in parallel and each operating at one bit per clock cycle.

摘要翻译： 源控制器提供n×a个信息位的块作为n个独立的行，每个行具有信息位。 行编码器具有耦合到源控制器的输出的输入，并且包括多个累加器，其布置成在一个时钟周期内处理信息位的m以产生行前向纠错FEC位。 至少一列列编码器具有耦合到源控制器的输出的输入，并且被布置成与行编码器并行地生成列FEC位。 多路复用器耦合到行编码器和列编码器的输出，并且适于串行地输出第n行的信息位，随后是n行中的每一行的第n行FEC位，随后由列编码器生成的附加的FEC位 。 术语n，m和a是大于1的整数。 在使用多个列编码器的情况下，优选并行地存在m个列编码器，并且每个时钟周期以一位操作。

公开(公告)号：US07613757B1

公开(公告)日：2009-11-03

申请号：US11336493

申请日：2006-01-20

申请人： Ayyoob Abbaszadeh ,  Rahman Altaf

发明人： Ayyoob Abbaszadeh ,  Rahman Altaf

IPC分类号： G06F1/02

CPC分类号： G06F1/025 ,  G06F7/582 ,  G06F7/584

摘要： The invention provides a system and method for generating a high rate pseudo-random noise (PN) code with a parallel PN generator. The method includes the operation of configuring L programmable PN generators to each output every Lth chip of a PN code. Select PN generators of the L PN generators can be configured to have their output delayed for a predetermined number of chips less than or equal to L when a fine slip is needed to allow the high rate PN code to be delayed for a set number of chips to synchronize the high rate PN code with another PN code. The outputs of each of the L programmable PN generators can be multiplexed to produce the high rate PN code.

摘要翻译： 本发明提供了一种用并行PN发生器产生高速伪随机噪声（PN）码的系统和方法。 该方法包括将PN可编程PN发生器配置到PN码的每个Lth码片的每个输出的操作。 选择PN发生器的PN发生器可以被配置为当需要微小的滑差以允许高速率PN码被延迟一定数量的芯片时将其输出延迟到小于或等于L的预定数量的芯片 以使高速率PN码与另一个PN码同步。 L个可编程PN发生器中的每一个的输出可以被多路复用以产生高速PN码。