公开(公告)号：US07271615B2

公开(公告)日：2007-09-18

申请号：US11301236

申请日：2005-12-12

申请人： Morteza Afghahi ,  Esin Terzioglu ,  Gil I. Winograd

发明人： Morteza Afghahi ,  Esin Terzioglu ,  Gil I. Winograd

IPC分类号： H03K17/16 ,  H03K19/003

CPC分类号： H03K19/0016

摘要： In one embodiment, NMOS transistors have their source coupled to a common source node such that the NMOS transistors conduct a leakage current if the common source node is grounded. To reduce this leakage current, the common source node is raised in potential. Similarly, PMOS transistors have their source coupled to a common source node such that the PMOS transistors conduct a leakage current if the common source node is charged to a power supply voltage VDD. To reduce this leakage current, the common source node is lowered in potential.

摘要翻译： 在一个实施例中，NMOS晶体管的源极耦合到公共源节点，使得如果公共源节点接地，则NMOS晶体管导通泄漏电流。 为了减少漏电流，公共源节点处于潜在状态。 类似地，PMOS晶体管的源极耦合到公共源节点，使得如果公共源节点被充电到电源电压VDD，则PMOS晶体管传导泄漏电流。 为了减少漏电流，公共源节点的电位降低。

公开(公告)号：US20050281108A1

公开(公告)日：2005-12-22

申请号：US11209866

申请日：2005-08-23

申请人： Esin Terzioglu ,  Morteza Afghahi ,  Mehdi Hatamian

发明人： Esin Terzioglu ,  Morteza Afghahi ,  Mehdi Hatamian

IPC分类号： G11C7/06 ,  G11C7/00

CPC分类号： G11C7/06

摘要： A hierarchical memory structure having memory cells, and sense amplifiers and decoders coupled with the memory cells to form first tier memory module, and subsequent tiers being formed by having (n-1)-tier memory modules, which are coupled with (n)-tier sense amplifiers and (n)-tier decoders. Also provided are a single-ended sense amplifier having sample-and-hold reference, and a charge-share limited-swing-driver sense amplifier; an asynchronously-resettable decoder; a wordline decoder having row redundancy; a redundancy device having redundant memory cells operated by a redundancy controller; a diffusion replica delay circuit; a high-precision delay measurement circuit; and a data transfer bus circuit imposing a limited voltage swing on a data bus. Methods are provided for a write-after-read operation without an interposed precharge cycle, and write-after-write operation with an interposed precharge cycle are provided, either operation being completed in less than one memory access cycle.

摘要翻译： 具有存储器单元的分层存储器结构，以及与存储器单元耦合以形成第一层存储器模块的读出放大器和解码器，以及随后的层通过具有（n-1）层的存储器模块形成，所述存储器模块与（n） - 层读出放大器和（n）层译码器。 还提供了具有采样保持基准的单端读出放大器和电荷共享限制摆幅驱动读出放大器; 异步复位解码器; 具有行冗余性的字线解码器; 具有由冗余控制器操作的冗余存储单元的冗余设备; 扩散复制延迟电路; 高精度延迟测量电路; 以及在数据总线上施加有限的电压摆幅的数据传输总线电路。 提供了用于在没有插入的预充电周期的写后读取操作的方法，并且提供了具有插入的预充电周期的写后写入操作，任一操作在少于一个存储器访问周期中完成。

公开(公告)号：US20050111258A1

公开(公告)日：2005-05-26

申请号：US10984077

申请日：2004-11-08

申请人： Esin Terzioglu ,  Morteza Afghahi ,  Gil Winograd

发明人： Esin Terzioglu ,  Morteza Afghahi ,  Gil Winograd

IPC分类号： G11C16/04 ,  G11C11/34

CPC分类号： G11C16/0433 ,  G11C2216/10

摘要： A non-volatile memory cell (10) includes a charge-storing node (16). An electrically insulating first layer (76) is coupled between the node and a source of a first voltage (22). An electrically insulating second layer (66) is coupled between the node and a source of a second voltage (20-21). The area of the first layer is smaller than the area of the second layer. A controller (90) is arranged to cause the first voltage to be greater than the second voltage so that charge is extracted from the node and is arranged to cause the second voltage to be greater than the first voltage so that charge is injected into the node.

摘要翻译： 非易失性存储单元（10）包括电荷存储节点（16）。 电绝缘的第一层（76）耦合在节点和第一电压源（22）之间。 电绝缘的第二层（66）耦合在节点和第二电压源（20-21）之间。 第一层的面积小于第二层的面积。 控制器（90）被布置成使得第一电压大于第二电压，使得从节点提取电荷并且被布置成使得第二电压大于第一电压，使得电荷被注入节点 。

公开(公告)号：US20050122246A1

公开(公告)日：2005-06-09

申请号：US11042006

申请日：2005-01-25

申请人： Esin Terzioglu ,  Morteza Afghahi ,  Gil Winograd

发明人： Esin Terzioglu ,  Morteza Afghahi ,  Gil Winograd

IPC分类号： G11C7/06 ,  G11C7/14 ,  H03M1/12

CPC分类号： G11C7/065 ,  G11C7/14

摘要： A digital memory system (30) includes a memory cell (52), a bit line (50), a transfer gate (60) a reference voltage generator (40), a sense amplifier (70) and a control circuit (80). The control circuit precharges the bit line to a bit line precharge voltage, which is sampled and stored. A corresponding reference voltage is generated after the bit line is isolated. The bit line and reference voltage are coupled to the sense amplifier so that a voltage is received based on charge stored in the memory cell. The sense amplifier then is isolated from the bit line and reference voltage and the sense amplifier is energized so that an output voltage is derived from the charge and reference voltage.

公开(公告)号：US20050018510A1

公开(公告)日：2005-01-27

申请号：US10925495

申请日：2004-08-24

申请人： Esin Terzioglu ,  Morteza Afghahi

发明人： Esin Terzioglu ,  Morteza Afghahi

IPC分类号： G11C7/06 ,  G11C7/00

CPC分类号： G11C7/06

摘要： A sense amplifier adapted to sense an input signal on global bitlines, having an amplifier offset cancellation network and an offset equalization network. The amplifier offset cancellation network mitigates an inherent offset signal value, a dynamic offset signal value, or both, yet produces a residual offset signal value, which is substantially eliminated by the offset equalization network. The sense amplifier also can include an isolation circuit to isolate the sense amplifier from the corresponding global bitlines when the sense amplifier is unused. Also, a charge-sharing circuit is used to share charge between the bitlines when the sense amplifier is activated, thus producing a limited voltage swing on the bit lines. The sense amplifier uses an amplifier offset cancellation network having multiple precharge-and-balance transistors, and an offset equalization network having at least one balancing transistor. Furthermore, the charge-sharing circuit includes a precharging circuit, and a charge reservoir, which selectively sources and sinks charge when the sense amplifier is used. The sense amplifier is a latch-type differential sense amplifier.

摘要翻译： 适于感测全局位线上的输入信号的读出放大器，具有放大器偏移消除网络和偏移均衡网络。 放大器偏移消除网络减轻固有偏移信号值，动态偏移信号值或二者，但是产生残余偏移信号值，其基本上被偏移均衡网络消除。 当读出放大器未使用时，读出放大器还可以包括隔离电路，以将读出放大器与对应的全局位线隔离。 此外，当感测放大器被激活时，电荷共享电路用于在位线之间共享电荷，从而在位线上产生有限的电压摆幅。 读出放大器使用具有多个预充电和平衡晶体管的放大器偏移消除网络，以及具有至少一个平衡晶体管的偏移均衡网络。 此外，电荷共享电路包括预充电电路和电荷储存器，当使用读出放大器时，电荷储存器选择性地源和吸收电荷。 读出放大器是锁存型差分读出放大器。

公开(公告)号：US20080224729A1

公开(公告)日：2008-09-18

申请号：US11857133

申请日：2007-09-18

申请人： Morteza Afghahi ,  Esin Terzioglu ,  Gil I. Winograd

发明人： Morteza Afghahi ,  Esin Terzioglu ,  Gil I. Winograd

IPC分类号： H03K17/16

CPC分类号： H03K19/0016

摘要： In one embodiment, NMOS transistors have their source coupled to a common source node such that the NMOS transistors conduct a leakage current if the common source node is grounded. To reduce this leakage current, the common source node is raised in potential. Similarly, PMOS transistors have their source coupled to a common source node such that the PMOS transistors conduct a leakage current if the common source node is charged to a power supply voltage VDD. To reduce this leakage current, the common source node is lowered in potential.

摘要翻译： 在一个实施例中，NMOS晶体管的源极耦合到公共源节点，使得如果公共源节点接地，则NMOS晶体管导通泄漏电流。 为了减少漏电流，公共源节点处于潜在状态。 类似地，PMOS晶体管的源极耦合到公共源节点，使得如果公共源节点被充电到电源电压VDD，则PMOS晶体管传导泄漏电流。 为了减少漏电流，公共源节点的电位降低。

公开(公告)号：US20070041259A1

公开(公告)日：2007-02-22

申请号：US11370738

申请日：2006-03-07

申请人： Esin Terzioglu ,  Gil Winograd ,  Morteza Afghahi

发明人： Esin Terzioglu ,  Gil Winograd ,  Morteza Afghahi

IPC分类号： G11C7/02

CPC分类号： G11C11/4091 ,  G11C7/02 ,  G11C7/065 ,  G11C7/12 ,  G11C11/401 ,  G11C11/4094 ,  G11C29/02 ,  G11C29/026 ,  G11C29/028 ,  G11C2207/2254 ,  H01L27/0207 ,  H01L27/10873 ,  H03K3/356034

摘要： In one embodiment, a sense amplifier includes: a differential amplifier adapted to amplify a voltage difference between a pair of bit lines; and a self-bias generation circuit adapted to reduce an offset bias in the differential amplifier with regard to the amplification of the voltage difference between the pair of bit lines.

摘要翻译： 在一个实施例中，读出放大器包括：差分放大器，适于放大一对位线之间的电压差; 以及自偏置生成电路，适于相对于所述一对位线之间的电压差的放大来减小所述差分放大器中的偏移偏置。

公开(公告)号：US20070040575A1

公开(公告)日：2007-02-22

申请号：US11301236

申请日：2005-12-12

申请人： Morteza Afghahi ,  Esin Terzioglu ,  Gil Winograd

发明人： Morteza Afghahi ,  Esin Terzioglu ,  Gil Winograd

IPC分类号： H03K19/003

CPC分类号： H03K19/0016

摘要： In one embodiment, NMOS transistors have their source coupled to a common source node such that the NMOS transistors conduct a leakage current if the common source node is grounded. To reduce this leakage current, the common source node is raised in potential. Similarly, PMOS transistors have their source coupled to a common source node such that the PMOS transistors conduct a leakage current if the common source node is charged to a power supply voltage VDD. To reduce this leakage current, the common source node is lowered in potential.

公开(公告)号：US20070165435A1

公开(公告)日：2007-07-19

申请号：US11431439

申请日：2006-05-10

申请人： Gil Winograd ,  Esin Terzioglu ,  Morteza Afghahi

发明人： Gil Winograd ,  Esin Terzioglu ,  Morteza Afghahi

IPC分类号： G11C15/00

CPC分类号： G11C15/04

摘要： In one embodiment, a CAM is provided that includes; a plurality of memory cells grouped to store a word, wherein the memory cells are organized into a plurality of ripple groups, each ripple group including a complex logic gate configured to determine whether a stored content for the ripple group's memory cells matches a corresponding portion of a comparand word if an enable input for the ripple group is asserted, each complex logic gate asserting an output if the determination indicates a match, the ripple groups being arranged from a first ripple group to a last ripple group such that the output from the first ripple group's complex logic gate functions as the enable input for a second ripple group's complex logic gate and so on such that an output from a next-to-last ripple group's complex logic gate functions as the enable input for the last ripple group's complex logic gate.

摘要翻译： 在一个实施例中，提供了一种CAM，其包括： 分组存储单词的多个存储单元，其中所述存储单元组织成多个纹波组，每个纹波组包括复合逻辑门，其配置用于确定所述纹波组的存储单元的存储内容是否与 一个比较字，如果纹波组的使能输入被断言，则每个复合逻辑门在该确定指示匹配时将输出置为有效，波纹组从第一纹波组布置到最后纹波组，使得来自第一 纹波组的复杂逻辑门用作第二纹波组的复杂逻辑门等的使能输入，使得来自下一个到最后纹波组的复杂逻辑门的输出用作最后纹波组的复杂逻辑门的使能输入 。

公开(公告)号：US20050146979A1

公开(公告)日：2005-07-07

申请号：US11058154

申请日：2005-02-15

申请人： Esin Terzioglu ,  Morteza Afghahi

发明人： Esin Terzioglu ,  Morteza Afghahi

IPC分类号： G11C7/06 ,  G11C8/00

CPC分类号： G11C7/06

摘要： A decoder providing asynchronous reset, redundancy, or both. an asynchronously-resettable decoder with redundancy. The decoder has a synchronous portion, responsive to a clocked signal; an asynchronous portion coupled with an asynchronous circuit; a feedback-resetting portion, which substantially isolates the synchronous portion from the asynchronous portion coupled with, and interposed between the synchronous portion in response to a asynchronous reset signal; a signal input; a first memory output coupled with a first memory cell group; a second memory output coupled with a second memory cell group; and a selector coupled between the signal input, the first memory output, and the second memory output. This decoder can be memory row-oriented, and thus provide an asynchronously-resettable row decoder with row redundancy, or an asynchronously-resettable column decoder with column redundancy.

摘要翻译： 提供异步复位，冗余或两者的解码器。 具有冗余的异步复位解码器。 解码器具有响应于时钟信号的同步部分; 与异步电路耦合的异步部分; 反馈复位部分，其响应于异步复位信号，基本上将同步部分与异步部分耦合并插入在同步部分之间; 信号输入; 与第一存储器单元组耦合的第一存储器输出; 与第二存储单元组耦合的第二存储器输出; 以及耦合在信号输入，第一存储器输出和第二存储器输出之间的选择器。 该解码器可以是面向行的存储器，并且因此提供具有行冗余的异步可重置行解码器，或者具有列冗余的异步可重置列解码器。