公开(公告)号：US20070109886A1

公开(公告)日：2007-05-17

申请号：US11616573

申请日：2006-12-27

Applicant: Esin Terzioglu ,  Gil Winograd ,  Cyrus Afghahi

Inventor： Esin Terzioglu ,  Gil Winograd ,  Cyrus Afghahi

IPC: G11C29/00

CPC classification number: G11C29/81 ,  G06F13/4086 ,  G11C7/06 ,  G11C7/18 ,  G11C11/41 ,  G11C11/419 ,  G11C29/808 ,  G11C29/848 ,  Y02D10/14 ,  Y02D10/151

Abstract: The present invention relates to a system and method for providing redundancy in a hierarchically memory, by replacing small blocks in such memory. The present invention provides such redundancy (i.e., replaces such small blocks) by either shifting predecoded lines or using a modified shifting predecoder circuit in the local predecoder block. In one embodiment, the hierarchal memory structure includes at least one active predecoder adapted to be shifted out of use; and at least one redundant predecoder adapted to be shifted in to use.

Abstract translation: 本发明涉及一种通过替换这种存储器中的小块来提供分层存储器中的冗余的系统和方法。 本发明通过移位预编码线路或者在本地预解码器块中使用修改的移位预解码器电路来提供这种冗余（即，替代这样的小块）。 在一个实施例中，分层存储器结构包括适于被移出使用的至少一个有源预解码器; 以及至少一个适于被移入使用的冗余预解码器。

公开(公告)号：US20050141325A1

公开(公告)日：2005-06-30

申请号：US11064218

申请日：2005-02-23

Applicant: Gil Winograd ,  Esin Terzioglu

Inventor： Gil Winograd ,  Esin Terzioglu

IPC: G06F13/40 ,  G11C7/18 ,  G11C11/419 ,  G11C29/00 ,  G11C8/00

CPC classification number: G11C29/808 ,  G06F13/4086 ,  G11C7/18 ,  G11C11/41 ,  G11C11/419 ,  G11C29/846 ,  G11C29/848

Abstract: The present invention relates to a system and method adapted to increase memory cell and memory architecture design yield. The present invention includes memory architecture having a decoder and a multi-bank memory. The decoder is adapted to decode addresses. The multi-bank memory interacts with the decoder, wherein the multi-bank memory includes at least one output data bit adapted to complete a word for a failing bank in the multi-bank memory.

Abstract translation: 本发明涉及适于增加存储器单元和存储器架构设计产量的系统和方法。 本发明包括具有解码器和多存储体存储器的存储器架构。 解码器适用于解码地址。 所述多存储体存储器与所述解码器交互，其中所述多存储体存储器包括适于完成所述多存储体存储器中的故障库的单词的至少一个输出数据位。

公开(公告)号：US20050111258A1

公开(公告)日：2005-05-26

申请号：US10984077

申请日：2004-11-08

Applicant: Esin Terzioglu ,  Morteza Afghahi ,  Gil Winograd

Inventor： Esin Terzioglu ,  Morteza Afghahi ,  Gil Winograd

IPC: G11C16/04 ,  G11C11/34

CPC classification number: G11C16/0433 ,  G11C2216/10

Abstract: A non-volatile memory cell (10) includes a charge-storing node (16). An electrically insulating first layer (76) is coupled between the node and a source of a first voltage (22). An electrically insulating second layer (66) is coupled between the node and a source of a second voltage (20-21). The area of the first layer is smaller than the area of the second layer. A controller (90) is arranged to cause the first voltage to be greater than the second voltage so that charge is extracted from the node and is arranged to cause the second voltage to be greater than the first voltage so that charge is injected into the node.

Abstract translation: 非易失性存储单元（10）包括电荷存储节点（16）。 电绝缘的第一层（76）耦合在节点和第一电压源（22）之间。 电绝缘的第二层（66）耦合在节点和第二电压源（20-21）之间。 第一层的面积小于第二层的面积。 控制器（90）被布置成使得第一电压大于第二电压，使得从节点提取电荷并且被布置成使得第二电压大于第一电压，使得电荷被注入节点 。

公开(公告)号：US07519862B2

公开(公告)日：2009-04-14

申请号：US10269201

申请日：2002-10-11

Applicant: Zeynep M. Toros ,  Esin Terzioglu ,  Gil Winograd

Inventor： Zeynep M. Toros ,  Esin Terzioglu ,  Gil Winograd

IPC: G06F11/00

CPC classification number: G06F11/27 ,  G01R31/31705 ,  G01R31/318555 ,  G11C5/04 ,  G11C29/16 ,  G11C2029/0401

Abstract: Aspects of the invention for testing and debugging an embedded device under test may include the step of loading an instruction into a parameterized shift register of a BIST module coupled to each one of a plurality of embedded memory modules comprising the embedded device under test. An identity of the loaded instruction may be determined subsequent to loading the instruction into the parameterized shift register. A plurality of test signals may be generated which correspond to the determined identity of the loaded instruction. In this regard, each of the generated plurality of test signals may control the execution of the testing and debugging of a corresponding one of each of the plurality of embedded memory modules that make up the embedded device under test.

Abstract translation: 用于测试和调试被测嵌入式设备的本发明的方面可以包括将指令加载到耦合到包括被测嵌入式设备的多个嵌入式存储器模块中的每一个的BIST模块的参数化移位寄存器中的步骤。 可以在将指令加载到参数化移位寄存器之后确定加载指令的身份。 可以生成与确定的加载指令的标识对应的多个测试信号。 在这点上，所生成的多个测试信号中的每个测试信号可以控制组成待测嵌入式设备的多个嵌入式存储器模块中的每一个的对应的一个测试和调试的执行。

公开(公告)号：US06728130B1

公开(公告)日：2004-04-27

申请号：US10447647

申请日：2003-05-29

Applicant: Morteza Cyrus Afghahi ,  Esin Terzioglu ,  Gil Winograd

Inventor： Morteza Cyrus Afghahi ,  Esin Terzioglu ,  Gil Winograd

IPC: G11C1100

CPC classification number: G11C11/412

Abstract: An SRAM cell eliminates the p-channel pull-up resistors to decrease its physical size. A tracking circuit generates a control signal used to ensure that the memory state is preserved during the idle state. The control signal controls the wordline voltage during the idle state to vary the leakage through the access transistors to ensure that current into the node through the access device is not exceeded by leakage current out of the output nodes through the storage devices. The tracking circuit control signal can also be used to vary the well to substrate bias voltage of the storage devices to decrease the leakage through the storage devices. The control signal can also be used to bias the supply rail voltage to which the storage devices are directly coupled to decrease the amount of leakage through the storage devices. The tracking circuit comprises a number of half configured memory cells that are placed in a state which mimics the stored state in a normal memory cell that would degrade during the idle state. A differential amplifier detects when the output state of the dummy cells have fallen below a predetermined reference voltage. The differential amplifier generates the control signal at a level required to restore the output state to at or near the reference voltage.

Abstract translation: SRAM单元消除了p沟道上拉电阻以减小其物理尺寸。 跟踪电路产生用于确保在空闲状态期间保持存储器状态的控制信号。 控制信号在空闲状态期间控制字线电压以改变通过存取晶体管的泄漏，以确保通过存储装置的输出节点之外的漏电流不会超过通过接入装置进入节点的电流。 跟踪电路控制信号也可以用于改变存储设备的阱到衬底偏置电压，以减少通过存储设备的泄漏。 控制信号也可以用于偏置存储装置直接耦合到的电源轨电压，以减少通过存储装置的泄漏量。 跟踪电路包括多个半配置的存储器单元，其被置于模拟在空闲状态期间将劣化的正常存储器单元中的存储状态的状态。 差分放大器检测虚拟单元的输出状态何时下降到预定参考电压以下。 差分放大器将输出状态恢复到等于或接近参考电压所需的电平。

公开(公告)号：US06563124B2

公开(公告)日：2003-05-13

申请号：US09814373

申请日：2001-03-21

Applicant: Lee Veneklasen ,  Vidhya Krishnamurthi ,  Gil Winograd

Inventor： Lee Veneklasen ,  Vidhya Krishnamurthi ,  Gil Winograd

IPC: H01J3706

CPC classification number: B82Y10/00 ,  B82Y40/00 ,  H01J37/30 ,  H01J37/3174 ,  H01J2237/03

Abstract: An electron beam apparatus is capable of registering an image on a substrate. The apparatus comprises a vacuum chamber having a wall. Electron beam source, modulator, and detector components are adapted to generate, modulate and detect an array of electron beams in the vacuum chamber. A circuit board passing through the wall of the vacuum chamber has a plurality of electrical traces to connect to the electron beam source, modulator, and detector components.

公开(公告)号：US07464295B2

公开(公告)日：2008-12-09

申请号：US10269635

申请日：2002-10-11

Applicant: Zevnep M. Toros ,  Esin Terzioglu ,  Gil Winograd

Inventor： Zevnep M. Toros ,  Esin Terzioglu ,  Gil Winograd

IPC: G06F11/00

CPC classification number: G06F11/27 ,  G01R31/31705 ,  G01R31/318555 ,  G11C29/16 ,  G11C2029/0401

Abstract: Aspects of the invention may include testing and debugging an embedded device under test. Testing and debugging and embedded device under test may include the step of loading an instruction into a parameterized shift register of each one of a plurality of BIST modules coupled to an individual one of a plurality of embedded memory modules comprising the embedded device under test. An identity of each of the instruction loaded into the parameterized shift register of each one of the plurality of BIST modules may subsequently be determined. A separate test signal may be generated from each one of the plurality of BIST modules corresponding to the determined identity of the instruction loaded in each one of the plurality of BIST modules, each one of the generated test signals causing control and execution of the testing and debugging of a corresponding one of each of the plurality of embedded memory modules comprising the embedded device under test.

Abstract translation: 本发明的方面可以包括测试和调试被测设备。 测试和调试以及被测试嵌入式设备可以包括将指令加载到多个BIST模块中的每个BIST模块的参数化移位寄存器中的步骤，所述BIST模块耦合到包括被测嵌入式设备的多个嵌入式存储器模块中的单独一个。 可以随后确定加载到多个BIST模块中的每一个的参数化移位寄存器中的每个指令的身份。 可以从多个BIST模块中的每个BIST模块生成对应于所确定的多个BIST模块中的每个BIST模块中加载的指令的身份的单独的测试信号，每个生成的测试信号引起测试的控制和执行， 包括被测嵌入式设备的多个嵌入式存储器模块中的每一个的对应的一个的调试。

公开(公告)号：US20070041259A1

公开(公告)日：2007-02-22

申请号：US11370738

申请日：2006-03-07

Applicant: Esin Terzioglu ,  Gil Winograd ,  Morteza Afghahi

Inventor： Esin Terzioglu ,  Gil Winograd ,  Morteza Afghahi

IPC: G11C7/02

CPC classification number: G11C11/4091 ,  G11C7/02 ,  G11C7/065 ,  G11C7/12 ,  G11C11/401 ,  G11C11/4094 ,  G11C29/02 ,  G11C29/026 ,  G11C29/028 ,  G11C2207/2254 ,  H01L27/0207 ,  H01L27/10873 ,  H03K3/356034

Abstract: In one embodiment, a sense amplifier includes: a differential amplifier adapted to amplify a voltage difference between a pair of bit lines; and a self-bias generation circuit adapted to reduce an offset bias in the differential amplifier with regard to the amplification of the voltage difference between the pair of bit lines.

Abstract translation: 在一个实施例中，读出放大器包括：差分放大器，适于放大一对位线之间的电压差; 以及自偏置生成电路，适于相对于所述一对位线之间的电压差的放大来减小所述差分放大器中的偏移偏置。

公开(公告)号：US20070040575A1

公开(公告)日：2007-02-22

申请号：US11301236

申请日：2005-12-12

Applicant: Morteza Afghahi ,  Esin Terzioglu ,  Gil Winograd

Inventor： Morteza Afghahi ,  Esin Terzioglu ,  Gil Winograd

IPC: H03K19/003

CPC classification number: H03K19/0016

Abstract: In one embodiment, NMOS transistors have their source coupled to a common source node such that the NMOS transistors conduct a leakage current if the common source node is grounded. To reduce this leakage current, the common source node is raised in potential. Similarly, PMOS transistors have their source coupled to a common source node such that the PMOS transistors conduct a leakage current if the common source node is charged to a power supply voltage VDD. To reduce this leakage current, the common source node is lowered in potential.

公开(公告)号：US20060220680A1

公开(公告)日：2006-10-05

申请号：US11447495

申请日：2006-06-06

Applicant: Esin Terzioglu ,  Gil Winograd

Inventor： Esin Terzioglu ,  Gil Winograd

IPC: H03K19/173

CPC classification number: G11C29/785 ,  G11C7/06 ,  G11C7/18 ,  G11C29/72 ,  G11C2207/002 ,  G11C2207/005 ,  H01L27/10

Abstract: The present invention relates to a system and method for increasing the manufacturing yield of a plurality of memory cells used in cell arrays. A programmable fuse, having both hardware and software elements, is used with the plurality of memory cells to indicate that at least one memory cell is unusable and should be shifted out of operation. The software programmable element includes a programmable register adapted to shift in an appropriate value indicating that at least one of the memory cells is flawed. The hardware element includes a fuse gated with the programmable register. Shifting is indicated either by software programmable fuse or hard fuse. Soft fuse registers may be chained together forming a shift register.