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公开(公告)号：US20090077506A1
公开(公告)日：2009-03-19
申请号：US12121135
申请日：2008-05-15
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G03F1/44 , G06F17/5045 , G06F17/5068 , G06F2217/12 , H01L27/0207 , Y02P90/265
摘要： Techniques are disclosed for optimizing the pattern density in the circuit layout design of a circuit layer. A layer in circuit design is analyzed to define empty regions that can be filled with fill polygons (referred to hereafter as “fill” regions). Next, a pattern of fill polygons is generated. After the fill polygons have been defined, the layout design for the layer is divided into separate areas or “windows,” and a target density for each window is determined. Once this target density for the window has been determined, the fill polygons required to most closely approach this target density are generated and added to the circuit layout design. This process may be repeated with progressively different (e.g., smaller) fill polygons, until each window meets or exceeds both the specified minimum density and complies with the specified maximum density gradient. Additionally, some implementations may allow a user to simultaneously optimize the density of multiple layers of a circuit by adding fill polygons to multiple layers of a circuit design simultaneously. Representations of sections of a multilayer fill structure will then be added to corresponding layers the circuit design until a specified target density is met.
摘要翻译： 公开了用于优化电路层的电路布局设计中的图案密度的技术。 分析电路设计中的层以定义可填充填充多边形（以下称为“填充”区域）的空区域。 接下来，生成填充多边形的图案。 在定义了填充多边形之后，层的布局设计被划分为单独的区域或“窗口”，并确定每个窗口的目标密度。 一旦确定了该窗口的目标密度，则生成最接近该目标密度所需的填充多边形，并将其添加到电路布局设计中。 该过程可以随着逐渐不同（例如较小的）填充多边形重复，直到每个窗口满足或超过规定的最小密度并且符合规定的最大密度梯度。 此外，一些实施方案可允许用户通过向电路设计的多个层同时添加填充多边形来同时优化电路的多层密度。 然后将多层填充结构的部分的表示添加到电路设计的相应层中，直到满足指定的目标密度。
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公开(公告)号：US20080034332A1
公开(公告)日：2008-02-07
申请号：US11743116
申请日：2007-05-01
申请人： Eugene Anikin , Fedor Pikus , John Stedman , Laurence Grodd , David Abercrombie
发明人： Eugene Anikin , Fedor Pikus , John Stedman , Laurence Grodd , David Abercrombie
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： Techniques are provided for optimizing the pattern density in the circuit layout design of a circuit layer. A layer in circuit design is analyzed to define fill regions that can be filled with fill polygons A pattern of fill polygons also is generated, to fill the fill regions. The layout design for the layer then is divided into separate areas or “windows,” and a target density for each window is determined. More particularly, each window is analyzed to determine a target density for the window that will satisfy specified density constraint values, such as a minimum density constraint, a maximum density constraint, or a maximum density gradient constraint. In some implementations, the target density will be the smallest density that will comply with each of the specified density value constraints. Once the target density for the window has been determined, the fill polygons required to most closely approach this target density are selected and added to the circuit layout design. With some implementations, this process may be repeated for fill polygons of different sizes or shapes.
摘要翻译： 提供了用于优化电路层的电路布局设计中的图案密度的技术。 分析电路设计中的层，以定义可填充填充多边形的填充区域。还生成填充多边形的图案，以填充填充区域。 然后将层的布局设计分为单独的区域或“窗口”，并确定每个窗口的目标密度。 更具体地，分析每个窗口以确定将满足指定密度约束值（例如最小密度约束，最大密度约束或最大密度梯度约束）的窗口的目标密度。 在一些实施方式中，目标密度将是符合每个特定密度值约束的最小密度。 一旦确定了窗口的目标密度，则选择最接近该目标密度所需的填充多边形并将其添加到电路布局设计中。 对于一些实现，对于不同大小或形状的填充多边形，可以重复该过程。
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公开(公告)号：US20110289471A1
公开(公告)日：2011-11-24
申请号：US13093828
申请日：2011-04-25
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G03F1/44 , G06F17/5045 , G06F17/5068 , G06F2217/12 , H01L27/0207 , Y02P90/265
摘要： Techniques are disclosed for optimizing the pattern density in the circuit layout design of a circuit layer. A layer in circuit design is analyzed to define empty regions that can be filled with fill polygons (referred to hereafter as “fill” regions). Next, a pattern of fill polygons is generated. After the fill polygons have been defined, the layout design for the layer is divided into separate areas or “windows,” and a target density for each window is determined. Once this target density for the window has been determined, the fill polygons required to most closely approach this target density are generated and added to the circuit layout design. This process may be repeated with progressively different (e.g., smaller) fill polygons, until each window meets or exceeds both the specified minimum density and complies with the specified maximum density gradient. Additionally, some implementations may allow a user to simultaneously optimize the density of multiple layers of a circuit by adding fill polygons to multiple layers of a circuit design simultaneously. Representations of sections of a multilayer fill structure will then be added to corresponding layers the circuit design until a specified target density is met.
摘要翻译： 公开了用于优化电路层的电路布局设计中的图案密度的技术。 分析电路设计中的层以定义可填充填充多边形（以下称为“填充”区域）的空区域。 接下来，生成填充多边形的图案。 在定义了填充多边形之后，层的布局设计被划分为单独的区域或“窗口”，并确定每个窗口的目标密度。 一旦确定了该窗口的目标密度，则生成最接近该目标密度所需的填充多边形，并将其添加到电路布局设计中。 该过程可以随着逐渐不同（例如较小的）填充多边形重复，直到每个窗口满足或超过规定的最小密度并且符合规定的最大密度梯度。 此外，一些实施方案可允许用户通过向电路设计的多个层同时添加填充多边形来同时优化电路的多层密度。 然后将多层填充结构的部分的表示添加到电路设计的相应层中，直到满足指定的目标密度。
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公开(公告)号：US09507902B2
公开(公告)日：2016-11-29
申请号：US13093828
申请日：2011-04-25
摘要： Techniques are disclosed for optimizing the pattern density in the circuit layout design of a circuit layer. A layer in circuit design is analyzed to define empty regions that can be filled with fill polygons (referred to hereafter as “fill” regions). Next, a pattern of fill polygons is generated. After the fill polygons have been defined, the layout design for the layer is divided into separate areas or “windows,” and a target density for each window is determined. Once this target density for the window has been determined, the fill polygons required to most closely approach this target density are generated and added to the circuit layout design. This process may be repeated with progressively different (e.g., smaller) fill polygons, until each window meets or exceeds both the specified minimum density and complies with the specified maximum density gradient. Additionally, some implementations may allow a user to simultaneously optimize the density of multiple layers of a circuit by adding fill polygons to multiple layers of a circuit design simultaneously. Representations of sections of a multilayer fill structure will then be added to corresponding layers the circuit design until a specified target density is met.
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公开(公告)号：US09652574B2
公开(公告)日：2017-05-16
申请号：US13093828
申请日：2011-04-25
CPC分类号： G06F17/5072 , G03F1/44 , G06F17/5045 , G06F17/5068 , G06F2217/12 , H01L27/0207 , Y02P90/265
摘要： Techniques are disclosed for optimizing the pattern density in the circuit layout design of a circuit layer. A layer in circuit design is analyzed to define empty regions that can be filled with fill polygons (referred to hereafter as “fill” regions). Next, a pattern of fill polygons is generated. After the fill polygons have been defined, the layout design for the layer is divided into separate areas or “windows,” and a target density for each window is determined. Once this target density for the window has been determined, the fill polygons required to most closely approach this target density are generated and added to the circuit layout design. This process may be repeated with progressively different (e.g., smaller) fill polygons, until each window meets or exceeds both the specified minimum density and complies with the specified maximum density gradient. Additionally, some implementations may allow a user to simultaneously optimize the density of multiple layers of a circuit by adding fill polygons to multiple layers of a circuit design simultaneously. Representations of sections of a multilayer fill structure will then be added to corresponding layers the circuit design until a specified target density is met.
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