-
公开(公告)号：US20090077506A1
公开(公告)日：2009-03-19
申请号：US12121135
申请日：2008-05-15
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G03F1/44 , G06F17/5045 , G06F17/5068 , G06F2217/12 , H01L27/0207 , Y02P90/265
摘要： Techniques are disclosed for optimizing the pattern density in the circuit layout design of a circuit layer. A layer in circuit design is analyzed to define empty regions that can be filled with fill polygons (referred to hereafter as “fill” regions). Next, a pattern of fill polygons is generated. After the fill polygons have been defined, the layout design for the layer is divided into separate areas or “windows,” and a target density for each window is determined. Once this target density for the window has been determined, the fill polygons required to most closely approach this target density are generated and added to the circuit layout design. This process may be repeated with progressively different (e.g., smaller) fill polygons, until each window meets or exceeds both the specified minimum density and complies with the specified maximum density gradient. Additionally, some implementations may allow a user to simultaneously optimize the density of multiple layers of a circuit by adding fill polygons to multiple layers of a circuit design simultaneously. Representations of sections of a multilayer fill structure will then be added to corresponding layers the circuit design until a specified target density is met.
摘要翻译： 公开了用于优化电路层的电路布局设计中的图案密度的技术。 分析电路设计中的层以定义可填充填充多边形（以下称为“填充”区域）的空区域。 接下来，生成填充多边形的图案。 在定义了填充多边形之后，层的布局设计被划分为单独的区域或“窗口”，并确定每个窗口的目标密度。 一旦确定了该窗口的目标密度，则生成最接近该目标密度所需的填充多边形，并将其添加到电路布局设计中。 该过程可以随着逐渐不同（例如较小的）填充多边形重复，直到每个窗口满足或超过规定的最小密度并且符合规定的最大密度梯度。 此外，一些实施方案可允许用户通过向电路设计的多个层同时添加填充多边形来同时优化电路的多层密度。 然后将多层填充结构的部分的表示添加到电路设计的相应层中，直到满足指定的目标密度。
-
公开(公告)号：US09652574B2
公开(公告)日：2017-05-16
申请号：US13093828
申请日：2011-04-25
CPC分类号： G06F17/5072 , G03F1/44 , G06F17/5045 , G06F17/5068 , G06F2217/12 , H01L27/0207 , Y02P90/265
摘要： Techniques are disclosed for optimizing the pattern density in the circuit layout design of a circuit layer. A layer in circuit design is analyzed to define empty regions that can be filled with fill polygons (referred to hereafter as “fill” regions). Next, a pattern of fill polygons is generated. After the fill polygons have been defined, the layout design for the layer is divided into separate areas or “windows,” and a target density for each window is determined. Once this target density for the window has been determined, the fill polygons required to most closely approach this target density are generated and added to the circuit layout design. This process may be repeated with progressively different (e.g., smaller) fill polygons, until each window meets or exceeds both the specified minimum density and complies with the specified maximum density gradient. Additionally, some implementations may allow a user to simultaneously optimize the density of multiple layers of a circuit by adding fill polygons to multiple layers of a circuit design simultaneously. Representations of sections of a multilayer fill structure will then be added to corresponding layers the circuit design until a specified target density is met.
-
公开(公告)号：US20110289471A1
公开(公告)日：2011-11-24
申请号：US13093828
申请日：2011-04-25
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G03F1/44 , G06F17/5045 , G06F17/5068 , G06F2217/12 , H01L27/0207 , Y02P90/265
摘要： Techniques are disclosed for optimizing the pattern density in the circuit layout design of a circuit layer. A layer in circuit design is analyzed to define empty regions that can be filled with fill polygons (referred to hereafter as “fill” regions). Next, a pattern of fill polygons is generated. After the fill polygons have been defined, the layout design for the layer is divided into separate areas or “windows,” and a target density for each window is determined. Once this target density for the window has been determined, the fill polygons required to most closely approach this target density are generated and added to the circuit layout design. This process may be repeated with progressively different (e.g., smaller) fill polygons, until each window meets or exceeds both the specified minimum density and complies with the specified maximum density gradient. Additionally, some implementations may allow a user to simultaneously optimize the density of multiple layers of a circuit by adding fill polygons to multiple layers of a circuit design simultaneously. Representations of sections of a multilayer fill structure will then be added to corresponding layers the circuit design until a specified target density is met.
摘要翻译： 公开了用于优化电路层的电路布局设计中的图案密度的技术。 分析电路设计中的层以定义可填充填充多边形（以下称为“填充”区域）的空区域。 接下来，生成填充多边形的图案。 在定义了填充多边形之后，层的布局设计被划分为单独的区域或“窗口”，并确定每个窗口的目标密度。 一旦确定了该窗口的目标密度，则生成最接近该目标密度所需的填充多边形，并将其添加到电路布局设计中。 该过程可以随着逐渐不同（例如较小的）填充多边形重复，直到每个窗口满足或超过规定的最小密度并且符合规定的最大密度梯度。 此外，一些实施方案可允许用户通过向电路设计的多个层同时添加填充多边形来同时优化电路的多层密度。 然后将多层填充结构的部分的表示添加到电路设计的相应层中，直到满足指定的目标密度。
-
公开(公告)号：US09507902B2
公开(公告)日：2016-11-29
申请号：US13093828
申请日：2011-04-25
摘要： Techniques are disclosed for optimizing the pattern density in the circuit layout design of a circuit layer. A layer in circuit design is analyzed to define empty regions that can be filled with fill polygons (referred to hereafter as “fill” regions). Next, a pattern of fill polygons is generated. After the fill polygons have been defined, the layout design for the layer is divided into separate areas or “windows,” and a target density for each window is determined. Once this target density for the window has been determined, the fill polygons required to most closely approach this target density are generated and added to the circuit layout design. This process may be repeated with progressively different (e.g., smaller) fill polygons, until each window meets or exceeds both the specified minimum density and complies with the specified maximum density gradient. Additionally, some implementations may allow a user to simultaneously optimize the density of multiple layers of a circuit by adding fill polygons to multiple layers of a circuit design simultaneously. Representations of sections of a multilayer fill structure will then be added to corresponding layers the circuit design until a specified target density is met.
-
公开(公告)号：US07930655B2
公开(公告)日：2011-04-19
申请号：US12117379
申请日：2008-05-08
申请人： ChandraSekhar Desu , Nima A. Behkami , Bruce J. Whitefield , David A. Abercrombie , David J. Sturtevant
发明人： ChandraSekhar Desu , Nima A. Behkami , Bruce J. Whitefield , David A. Abercrombie , David J. Sturtevant
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A graphical profile map for integrated circuits on a substrate. The graphical profile map includes a depiction of die placement boundaries and shot placement boundaries for the integrated circuits on the substrate. Also included are integrated circuit property information contours, where the contours are not limited to either of the die placement boundaries or the shot placement boundaries. In this manner, three key pieces of information for the integrated circuits are presented, including integrated circuit property information, die placement, and shot placement. Because these three pieces of information are presented in a graphical form, it is much easier to interpret the information. For example, it is much easier to determine which shot and die placements have properties that are at risk, and which shot and die placements have adequate property profiles.
摘要翻译： 衬底上集成电路的图形配置图。 图形轮廓图包括对基片上的集成电路的管芯放置边界和镜头放置边界的描绘。 还包括集成电路属性信息轮廓，其中轮廓不限于管芯放置边界或射击放置边界中的任何一个。 以这种方式，提供了用于集成电路的三个关键信息，包括集成电路属性信息，管芯放置和射击放置。 因为这三条信息以图形形式呈现，所以解释信息要容易得多。 例如，确定哪些投篮和投篮位置具有处于风险中的属性以及哪些投篮和投篮位置具有足够的财产配置文件将变得更加容易。
-
公开(公告)号：US07395522B2
公开(公告)日：2008-07-01
申请号：US10801310
申请日：2004-03-16
申请人： ChandraSekhar Desu , Nima A. Behkami , Bruce J. Whitefield , David A. Abercrombie , David J. Sturtevant
发明人： ChandraSekhar Desu , Nima A. Behkami , Bruce J. Whitefield , David A. Abercrombie , David J. Sturtevant
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A graphical profile map for integrated circuits on a substrate. The graphical profile map includes a depiction of die placement boundaries and shot placement boundaries for the integrated circuits on the substrate. Also included are integrated circuit property information contours, where the contours are not limited to either of the die placement boundaries or the shot placement boundaries. In this manner, three key pieces of information for the integrated circuits are presented, including integrated circuit property information, die placement, and shot placement. Because these three pieces of information are presented in a graphical form, it is much easier to interpret the information. For example, it is much easier to determine which shot and die placements have properties that are at risk, and which shot and die placements have adequate property profiles.
摘要翻译： 衬底上集成电路的图形配置图。 图形轮廓图包括对基片上的集成电路的管芯放置边界和镜头放置边界的描绘。 还包括集成电路属性信息轮廓，其中轮廓不限于管芯放置边界或射击放置边界中的任何一个。 以这种方式，提供了用于集成电路的三个关键信息，包括集成电路属性信息，管芯放置和射击放置。 因为这三条信息以图形形式呈现，所以解释信息要容易得多。 例如，确定哪些投篮和投篮位置具有处于风险中的属性以及哪些投篮和投篮位置具有足够的财产配置文件将变得更加容易。
-
公开(公告)号：US07039556B2
公开(公告)日：2006-05-02
申请号：US10867003
申请日：2004-06-14
CPC分类号： G05B19/41875 , G05B2219/37224 , G05B2219/45031 , Y02P90/22
摘要： A system for analyzing fabrication processes, such as analyzing device yield on a substrate. An input accesses fabrication information, where the fabrication information includes at least one of an dependent variable that is associated with substrate location information, and at least one independent variable that is associated with at least one of the fabrication processes. Desired portions of the substrate information are selected, based on at least one of the independent variable and the dependent variable. A substrate profile is produced, based on the desired portions of the fabrication information.
摘要翻译： 用于分析制造工艺的系统，例如分析衬底上的器件产量。 输入访问制造信息，其中制造信息包括与衬底位置信息相关联的因变量中的至少一个以及与至少一个制造过程相关联的至少一个独立变量。 基于自变量和因变量中的至少一个，选择衬底信息的期望部分。 基于制造信息的期望部分产生衬底轮廓。
-
公开(公告)号：US06658361B1
公开(公告)日：2003-12-02
申请号：US09974008
申请日：2001-10-10
IPC分类号： G06F1900
CPC分类号： H01L22/20
摘要： A method for determining an effective fatal defect count based on defects in a plurality of inspected integrated circuits includes acquiring defect information related to defects in the integrated circuits, and assigning defect weight values to each of the defects based on the defect information. The defect weight values are in N number of defect weight value ranges, including a lowest and a highest defect weight value range. For each integrated circuit, a heaviest defect is determined, where the heaviest defect is the defect on each integrated circuit having a highest defect weight value. For each of the N number of defect weight value ranges, a total number T(n) of the heaviest defects having a defect weight value within a defect weight value range n is determined, where n equals one to N. A weighted total defect count TW(n) is determined by weighting the total number T(n) for each of the defect weight value ranges according to a weighting function FP(n) which approaches zero at the lowest defect weight value range and approaches one at the highest defect weight value range. The effective fatal defect count is determined by summing the values of TW(n) for the N number of defect weight value ranges. The defect weight values are preferably assigned to each of the defects based on defect size, where the smallest defects are in the lowest defect weight value range, and the largest defects are in the highest defect weight value range. Since the heaviest only weighting gives more weight to large defects, the effective fatal defect count is weighted more heavily toward larger defects.
摘要翻译： 基于多个检查集成电路中的缺陷来确定有效致命缺陷计数的方法包括获取与集成电路中的缺陷相关的缺陷信息，并且基于缺陷信息为每个缺陷分配缺陷权重值。 缺陷重量值为N个缺陷重量值范围，包括最低和最高缺陷重量值范围。 对于每个集成电路，确定最重的缺陷，其中最重的缺陷是具有最高缺陷重量值的每个集成电路上的缺陷。 对于N个缺陷重量值范围中的每一个，确定具有缺陷重量值范围n内的缺陷重量值的最重缺陷的总数T（n），其中n等于1至N.加权总缺陷计数 通过根据在最低缺陷重量值范围接近零的加权函数FP（n）对每个缺陷权重值范围加权总数T（n）来确定TW（n），并接近最高缺陷权重处的一个 价值范围。 通过对N个缺陷重量值范围的TW（n）的值求和来确定有效的致命缺陷计数。 缺陷重量值优选地基于缺陷尺寸分配给每个缺陷，其中最小缺陷处于最低缺陷重量值范围，并且最大缺陷处于最高缺陷重量值范围。 由于最重的权重对较大的缺陷给予了更大的重视，所以有效的致命缺陷计数对较大的缺陷加权更大。
-
9.发明授权Method for forming a line-on-line multi-level metal interconnect structure for use in integrated circuits 失效用于形成集成电路中使用的在线多级金属互连结构的方法
公开(公告)号：US5937324A
公开(公告)日：1999-08-10
申请号：US41646
申请日：1998-03-13
IPC分类号： H01L21/768 , H01L23/522 , H01L23/528 , H01L23/532
CPC分类号： H01L23/5283 , H01L23/5226 , H01L23/53223 , H01L2924/0002
摘要： A method of manufacturing a semiconductor component with a multi-level interconnect system includes providing a substrate (11), fabricating a device (12) in the substrate (11), forming an interconnect layer (15) over the substrate (11), depositing a dielectric layer (20) over the interconnect layer (15), depositing a separate interconnect layer (21) over the dielectric layer (20), etching a via (31) in the separate interconnect layer (21) and in the dielectric layer (20), and depositing a different interconnect layer (40) over the separate interconnect layer (21) and in the via (31) wherein the another interconnect layer (40) electrically couples the interconnect layer (15) and the separate interconnect layer (21).
摘要翻译： 一种制造具有多级互连系统的半导体部件的方法包括：提供衬底（11），在衬底（11）中制造器件（12），在衬底（11）上形成互连层（15），沉积 在所述互连层（15）上的电介质层（20），在所述电介质层（20）上沉积单独的互连层（21），蚀刻所述单独的互连层（21）和介电层 20），以及在所述分离的互连层（21）上和所述通孔（31）中沉积不同的互连层（40），其中所述另一互连层（40）将所述互连层（15）和所述分离的互连层 ）。
-
公开(公告)号：US08612919B2
公开(公告)日：2013-12-17
申请号：US11986564
申请日：2007-11-20
CPC分类号： G06F17/5081
摘要： An analog design-rule-check tool analyzes a microdevice design, such as an integrated circuit design, to identify occurrences of geometric elements that share a specified relationship. When the tool identifies such an occurrence of these geometric elements, it will associate or “cluster” these geometric elements together into an identifiable unit. For specified “clusters” of geometric elements, the analog design-rule-check tool will then determine the value of a measurement or measurements required by a user. Once the analog design-rule-check tool has determined the necessary measurement values, it will use those values to evaluate the function describing a model.
摘要翻译： 模拟设计规则检查工具分析微设计设计，例如集成电路设计，以识别共享指定关系的几何元素的出现。 当工具识别这些几何元素的这种出现时，它将将这些几何元素相关联或“聚集”到一个可识别的单元中。 对于几何元素的特定“簇”，模拟设计规则检查工具将确定用户所需的测量值或测量值。 一旦模拟设计规则检查工具确定了必要的测量值，它将使用这些值来评估描述模型的功能。
-
-
-
-
-
-
-
-
-
搜索结果
16 条记录 (耗时 0.03 秒)
