公开(公告)号：US10657014B2

公开(公告)日：2020-05-19

申请号：US15901330

申请日：2018-02-21

Applicant: Everspin Technologies, Inc.

Inventor： Kurt Baty ,  Terry Van Hulett

IPC: G06F11/00 ,  G06F11/20 ,  G06F11/10 ,  G11C29/00 ,  G11C29/44 ,  G06F11/07 ,  G06F11/30

Abstract: The present disclosure is drawn to, among other things, a method of managing a memory device. In some aspects, the method includes scanning a first memory region for bit errors; in response to detecting one or more bit errors in the first memory region, incrementing a counter associated with the first memory region based on the number of bit errors detected; comparing a total number of bit errors against a threshold, wherein the total number of bit errors is identified from the first counter; and, if the total number of bit errors exceeds the threshold, restricting access to the first memory region by mapping an address corresponding to the first memory region to a second memory region.

公开(公告)号：US10348333B2

公开(公告)日：2019-07-09

申请号：US15711877

申请日：2017-09-21

Applicant: EVERSPIN TECHNOLOGIES, INC.

Inventor： Kurt Baty

IPC: H03M13/29 ,  G11C29/52 ,  G06F11/10 ,  H03M13/05

Abstract: Apparatus, methods, and systems are disclosed for performing bit error correction on a data stream. In some aspects, the described systems and methods may include a plurality of memory devices, a first interface, and a field programmable gate array. The field programmable gate array may include a memory controller and a plurality of re-programmable gates. At least one of the re-programmable gates may be configured as a read-only memory (ROM) to store a syndrome decode memory table, wherein the syndrome decode memory table may be configured to perform bit error correction on the data stream being read and/or written to at least one memory device of the plurality of memory devices via the first interface.

公开(公告)号：US10102064B1

公开(公告)日：2018-10-16

申请号：US14923565

申请日：2015-10-27

Applicant: Everspin Technologies, Inc.

Inventor： Kurt Baty

IPC: H03M13/00 ,  H03M13/37 ,  G06F11/10 ,  H03M13/15 ,  H03M13/13

Abstract: A memory device includes one or more memory arrays and a quad bit error correction circuit. The quad bit error correction circuit may include a first layer error correction circuit and a second layer error correction circuit. The first layer error correction circuit may be configured to generate a Hamming correction bit vector, and the second layer error correction circuit may be configured to generate a Golay correction bit vector. The Hamming correction bit vector and the Golay correction bit vector may be used to identify up to four correctable bit errors in data to be stored in the one more memory arrays.