公开(公告)号：US10027330B1

公开(公告)日：2018-07-17

申请号：US15889740

申请日：2018-02-06

Applicant: FARADAY TECHNOLOGY CORPORATION

Inventor： Zhao-Yong Zhang ,  Shih-Chin Lin ,  Wei-Chang Wang

IPC: H03K19/20 ,  G06F17/50

Abstract: An arbitrating circuit includes a first NOR gate, a second NOR gate, four resistors and a pull-up circuit. The first transistor is connected with the first node and the second node, and generates a first acknowledging signal. The second transistor is connected with a supply voltage, the second node and the first transistor. The third transistor is connected with the first node and second node, and generates a second acknowledging signal. The fourth transistor is connected with the supply voltage, the first node and the third transistor. The pull-up circuit is connected with the first node, the second node, the first NOR gate and the second NOR gate. If both of the first request signal and the second request signal have a low logic level, a voltage at the second node is pulled up to a high logic level by the pull-up circuit.