公开(公告)号：US10027330B1

公开(公告)日：2018-07-17

申请号：US15889740

申请日：2018-02-06

Applicant: FARADAY TECHNOLOGY CORPORATION

Inventor： Zhao-Yong Zhang ,  Shih-Chin Lin ,  Wei-Chang Wang

IPC: H03K19/20 ,  G06F17/50

Abstract: An arbitrating circuit includes a first NOR gate, a second NOR gate, four resistors and a pull-up circuit. The first transistor is connected with the first node and the second node, and generates a first acknowledging signal. The second transistor is connected with a supply voltage, the second node and the first transistor. The third transistor is connected with the first node and second node, and generates a second acknowledging signal. The fourth transistor is connected with the supply voltage, the first node and the third transistor. The pull-up circuit is connected with the first node, the second node, the first NOR gate and the second NOR gate. If both of the first request signal and the second request signal have a low logic level, a voltage at the second node is pulled up to a high logic level by the pull-up circuit.

公开(公告)号：US20150138869A1

公开(公告)日：2015-05-21

申请号：US14180703

申请日：2014-02-14

Applicant: FARADAY TECHNOLOGY CORPORATION

Inventor： Chih-Kang Chiu ,  Wei-Chang Wang ,  Sheng-Tai Young

IPC: G11C17/12

CPC classification number: G11C17/123 ,  G11C17/12 ,  G11C17/18

Abstract: A non-volatile memory includes a memory unit. The memory unit includes a first word line, a second word line, a control line, a logic circuit, a bit line, a first cell, and a second cell. The logic circuit has a first input terminal connected to the first word line, a second input terminal connected to the second word line, and an output terminal connected to the control line. The first cell has a control terminal connected to the first word line, a first terminal connected to the control line, and a second terminal selectively connected to the bit line. The second cell has a control terminal connected to the second word line, a first terminal connected to the control line, and a second terminal selectively connected to the bit line.

Abstract translation: 非易失性存储器包括存储器单元。 存储单元包括第一字线，第二字线，控制线，逻辑电路，位线，第一单元和第二单元。 逻辑电路具有连接到第一字线的第一输入端，连接到第二字线的第二输入端和连接到控制线的输出端。 第一单元具有连接到第一字线的控制端子，连接到控制线的第一端子和选择性地连接到位线的第二端子。 第二单元具有连接到第二字线的控制端子，连接到控制线的第一端子和选择性地连接到位线的第二端子。