公开(公告)号：US20150332069A1

公开(公告)日：2015-11-19

申请号：US14809683

申请日：2015-07-27

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Joseph C. Circello ,  Daniel M. McCarthy ,  John D. Mitchell ,  Peter J. Wilson ,  John J. Vaglica

IPC: G06F21/85 ,  G06F21/74 ,  G06F12/14

CPC classification number: G06F21/85 ,  G06F12/1458 ,  G06F21/74

Abstract: A storage location of a device that can be configured to act as a master in a particular security mode, such as a Direct Memory Access (DMA) having one or more channels, can be programmed to indicate a security indicator to be provided when configured to operate as a master device.

Abstract translation: 可以对可以被配置为在特定安全模式（例如具有一个或多个信道的直接存储器访问（DMA））中作为主机的设备的存储位置进行编程，以指示当被配置为 作为主设备运行。

公开(公告)号：US09824242B2

公开(公告)日：2017-11-21

申请号：US14809683

申请日：2015-07-27

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Joseph C. Circello ,  Daniel M. McCarthy ,  John D. Mitchell ,  Peter J. Wilson ,  John J. Vaglica

IPC: G06F21/85 ,  G06F12/14 ,  G06F21/74

CPC classification number: G06F21/85 ,  G06F12/1458 ,  G06F21/74

Abstract: A storage location of a device that can be configured to act as a master in a particular security mode, such as a Direct Memory Access (DMA) having one or more channels, can be programmed to indicate a security indicator to be provided when configured to operate as a master device.

公开(公告)号：US20160314030A1

公开(公告)日：2016-10-27

申请号：US14694601

申请日：2015-04-23

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Peter J. Wilson ,  Brian C. Kahne

IPC: G06F9/54

CPC classification number: G06F9/546

Abstract: A processing system includes a first processing system element, and a second processing system element configured to communicate with the first processing system. The second processing system element includes a set of messaging queues. Each of the messaging queues includes one or more entries for storing data, a set of delegate queue addresses associated with one of the set of messaging queues; and a delegate queue associated with the set of messaging queues. The delegate queue includes a set of entries corresponding to the delegate queue addresses, and each of the entries of the delegate queue indicates whether a corresponding one of the set of messaging queues is storing data.

Abstract translation: 处理系统包括第一处理系统元件和被配置为与第一处理系统通信的第二处理系统元件。 第二处理系统元件包括一组消息队列。 每个消息队列包括用于存储数据的一个或多个条目，与该组消息队列之一相关联的一组委托队列地址; 以及与该组消息队列相关联的委托队列。 委托队列包括与委托队列地址对应的一组条目，代理队列的每个条目指示该组消息队列中相应的一个是否存储数据。

公开(公告)号：US09753790B2

公开(公告)日：2017-09-05

申请号：US14828722

申请日：2015-08-18

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Peter J. Wilson ,  Brian C. Kahne

IPC: G06F9/54 ,  G06F9/30

CPC classification number: G06F9/546 ,  G06F9/30087

Abstract: A method of handling requests between contexts in a processing system includes, in a current context of a source processing system element (PSE): executing a send-and rendezvous instruction that specifies a destination PSE, a queue address in the destination PSE, a set of source registers, and a set of receive registers; and sending a send-and-rendezvous message (SRM) to the destination PSE, wherein the SRM includes an address of the destination PSE, a destination queue address, a source PSE address, and an identifier of the current context in the source PSE.

公开(公告)号：US09507654B2

公开(公告)日：2016-11-29

申请号：US14694601

申请日：2015-04-23

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Peter J. Wilson ,  Brian C. Kahne

IPC: G06F13/00 ,  G06F9/54

CPC classification number: G06F9/546

Abstract: A processing system includes a first processing system element, and a second processing system element configured to communicate with the first processing system. The second processing system element includes a set of messaging queues. Each of the messaging queues includes one or more entries for storing data, a set of delegate queue addresses associated with one of the set of messaging queues; and a delegate queue associated with the set of messaging queues. The delegate queue includes a set of entries corresponding to the delegate queue addresses, and each of the entries of the delegate queue indicates whether a corresponding one of the set of messaging queues is storing data.

Abstract translation: 处理系统包括第一处理系统元件和被配置为与第一处理系统通信的第二处理系统元件。 第二处理系统元件包括一组消息队列。 每个消息队列包括用于存储数据的一个或多个条目，与该组消息队列之一相关联的一组委托队列地址; 以及与该组消息队列相关联的委托队列。 委托队列包括与委托队列地址对应的一组条目，代理队列的每个条目指示该组消息队列中相应的一个是否存储数据。

公开(公告)号：US20160004536A1

公开(公告)日：2016-01-07

申请号：US14321957

申请日：2014-07-02

Applicant: Freescale Semiconductor Inc.

Inventor： Peter J. Wilson ,  Brian C. Kahne ,  Jeffrey W. Scott

IPC: G06F9/38

CPC classification number: G06F9/30167 ,  G06F9/35 ,  G06F9/3814 ,  G06F9/3832

Abstract: Disclosed is a digital processor comprising an instruction memory having a first input, a second input, a first output, and a second output. A program counter register is in communication with the first input of the instruction memory. The program counter register is configured to store an address of an instruction to be fetched. A data pointer register is in communication with the second input of the instruction memory. The data pointer register is configured to store an address of a data value in the instruction memory. An instruction buffer is in communication with the first output of the instruction memory. The instruction buffer is arranged to receive an instruction according to a value at the program counter register. A data buffer is in communication with the second output of the instruction memory. The data buffer is arranged to receive a data value according to a value at the data pointer register.

Abstract translation: 公开了一种数字处理器，包括具有第一输入，第二输入，第一输出和第二输出的指令存储器。 程序计数器寄存器与指令存储器的第一输入端通信。 程序计数器寄存器被配置为存储要获取的指令的地址。 数据指针寄存器与指令存储器的第二输入端通信。 数据指针寄存器被配置为在指令存储器中存储数据值的地址。 指令缓冲器与指令存储器的第一输出端通信。 指令缓冲器被配置为根据程序计数器寄存器的值接收指令。 数据缓冲器与指令存储器的第二输出端通信。 数据缓冲器被设置为根据数据指针寄存器上的值接收数据值。