公开(公告)号：US10108467B2

公开(公告)日：2018-10-23

申请号：US14695633

申请日：2015-04-24

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Jeffrey W. Scott ,  William C. Moyer ,  Quyen Pho

IPC: G06F3/00 ,  G06F9/52 ,  G06F12/0875 ,  G06F12/0862 ,  G06F9/38 ,  G06F13/38

Abstract: A data processing system includes an instruction pipeline, a bus interface unit, and a cache. The instruction pipeline is configured to assert a discard signal when a speculative read request is determined to have been mispredicted. The speculative read request has a corresponding access address. The bus interface unit is configured to communicate with an external system interconnect. The cache includes a cache array and cache control circuitry. The cache control circuitry is configured to receive the discard signal from the instruction pipeline and, when the discard signal is asserted after the access address has been provided to the external system interconnect by the bus interface unit in response to a determination by the cache control circuitry that the access address missed in the cache array, selectively store the read information returned from the access address into the cache array.

公开(公告)号：US10445133B2

公开(公告)日：2019-10-15

申请号：US15060692

申请日：2016-03-04

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Jonathan J. Gamoneda ,  Jehoda Refaeli ,  Jeffrey W. Scott

IPC: G06F9/48 ,  G06F11/36

Abstract: A method for managing thread execution in a processing system is provided. The method includes setting a first watchpoint, and generating a first watchpoint trigger corresponding to the first watchpoint. In response to the first watchpoint trigger, execution of a first thread is controlled in accordance with a value stored in a first control register. Controlling the first thread may further include disabling execution of the first thread. The disabling execution of the first thread may occur within the first watchpoint region.

公开(公告)号：US20160004536A1

公开(公告)日：2016-01-07

申请号：US14321957

申请日：2014-07-02

Applicant: Freescale Semiconductor Inc.

Inventor： Peter J. Wilson ,  Brian C. Kahne ,  Jeffrey W. Scott

IPC: G06F9/38

CPC classification number: G06F9/30167 ,  G06F9/35 ,  G06F9/3814 ,  G06F9/3832

Abstract: Disclosed is a digital processor comprising an instruction memory having a first input, a second input, a first output, and a second output. A program counter register is in communication with the first input of the instruction memory. The program counter register is configured to store an address of an instruction to be fetched. A data pointer register is in communication with the second input of the instruction memory. The data pointer register is configured to store an address of a data value in the instruction memory. An instruction buffer is in communication with the first output of the instruction memory. The instruction buffer is arranged to receive an instruction according to a value at the program counter register. A data buffer is in communication with the second output of the instruction memory. The data buffer is arranged to receive a data value according to a value at the data pointer register.

Abstract translation: 公开了一种数字处理器，包括具有第一输入，第二输入，第一输出和第二输出的指令存储器。 程序计数器寄存器与指令存储器的第一输入端通信。 程序计数器寄存器被配置为存储要获取的指令的地址。 数据指针寄存器与指令存储器的第二输入端通信。 数据指针寄存器被配置为在指令存储器中存储数据值的地址。 指令缓冲器与指令存储器的第一输出端通信。 指令缓冲器被配置为根据程序计数器寄存器的值接收指令。 数据缓冲器与指令存储器的第二输出端通信。 数据缓冲器被设置为根据数据指针寄存器上的值接收数据值。

公开(公告)号：US20170255485A1

公开(公告)日：2017-09-07

申请号：US15060692

申请日：2016-03-04

Applicant: FREESCALE SEMICONDUCTOR INC.

Inventor： Jonathan J. Gamoneda ,  Jehoda Refaeli ,  Jeffrey W. Scott

IPC: G06F9/48 ,  G06F9/38

CPC classification number: G06F9/485 ,  G06F11/34 ,  G06F11/3636

Abstract: A method for managing thread execution in a processing system is provided. The method includes setting a first watchpoint, and generating a first watchpoint trigger corresponding to the first watchpoint. In response to the first watchpoint trigger, execution of a first thread is controlled in accordance with a value stored in a first control register. Controlling the first thread may further include disabling execution of the first thread. The disabling execution of the first thread may occur within the first watchpoint region.

公开(公告)号：US09483272B2

公开(公告)日：2016-11-01

申请号：US14502027

申请日：2014-09-30

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Jeffrey W. Scott ,  William C. Moyer ,  Alistair P. Robertson

IPC: G06F9/00 ,  G06F9/44 ,  G06F9/38 ,  G06F9/32

CPC classification number: G06F9/3806 ,  G06F9/322 ,  G06F9/3851

Abstract: A processor is configured to execute instructions of a first thread and a second thread. A first return stack corresponds to the first thread, and a second return stack to the second thread. Control circuitry pushes a return address to the first return stack in response to a branch to subroutine instruction in the first thread. If the first return stack is full and borrowing is not enabled by the borrow enable indicator, the control circuitry removes an oldest return address from the first return stack and not store the removed oldest return address in the second return stack. If the first return stack is full and borrowing is enabled by the borrow enable indicator and the second thread is not enabled, the control circuitry removes the oldest return address from the first return stack and push the removed oldest return address onto the second return stack.

Abstract translation: 处理器被配置为执行第一线程和第二线程的指令。 第一个返回栈对应于第一个线程，第二个返回栈对应于第二个线程。 响应于第一个线程中的子程序指令的分支，控制电路将返回地址推送到第一个返回栈。 如果第一个返回堆栈已满并且借位启用指示器未启用借用，则控制电路从第一个返回堆栈中删除最旧的返回地址，而不将删除的最旧的返回地址存储在第二个返回栈中。 如果第一个返回堆栈已满，并借用启用指示符启用借用，并且第二个线程未启用，则控制电路从第一个返回堆栈中删除最早的返回地址，并将删除的最旧的返回地址推送到第二个返回栈。

公开(公告)号：US09047400B2

公开(公告)日：2015-06-02

申请号：US13827004

申请日：2013-03-14

Applicant: Freescale Semiconductor, Inc.

Inventor： Jeffrey W. Scott ,  William C. Moyer

IPC: G06F11/00 ,  G06F11/34

CPC classification number: G06F11/3495 ,  G06F11/3636 ,  G06F11/3656

Abstract: During a debug mode of operation of a data processor, it is determined at the data processor that a watchpoint event has occurred, and in response, an operating condition of a trace FIFO that stores trace information not yet communicated to a debugger is changed. For example, the occurrence of a FIFO flush watchpoint results in trace information being selectively flushed from the trace FIFO based on a state of the FIFO before the trace information has been communicated to a trace analyzer.

Abstract translation: 在数据处理器的调试操作模式期间，在数据处理器确定观察点事件已经发生，并且作为响应，存储跟尚未通信给调试器的跟踪信息的跟踪FIFO的操作条件被改变。 例如，FIFO跟踪观察点的发生导致在跟踪信息已被传送到跟踪分析器之前，基于FIFO的状态，从跟踪FIFO中选择性地刷新跟踪信息。