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1.发明申请公开(公告)号：US20210214447A1
公开(公告)日：2021-07-15
申请号：US17055499
申请日：2019-05-10
发明人： Ke YU , Jingkang SHEN , Tao MENG , Jinpeng PEI , Lanping MA , Xin WANG , Rui JIN , Zhiyan DU , Lin CHEN , Ting YU , Yongliang ZHANG
摘要： Disclosed are a new AXL-targeting monoclonal antibody and antibody-drug conjugate. Also disclosed is a method for preparing said antibody and antibody-drug conjugate. The AXL antibody of the present invention can bind with purified humanAXL protein and multiple AXL on tumor cell surface with high effectiveness and high specificity. Said humanized antibody also has high affinity and low immunogenicity. Said AXL antibody-drug conjugate has markable performance against tumors having high AXL expression.
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公开(公告)号：US20180079749A1
公开(公告)日：2018-03-22
申请号：US15561003
申请日：2016-03-24
申请人： SHANGHAI INSTITUTE OF MATERIA MEDICA,CHINESE ACADEMY OF SCIENCES , SHANDONG LUOXIN PHARMACEUTICAL GROUP STOCK CO., LTD.
发明人： Jingkang SHEN , Tao MENG , Ting YU , Lanping MA , Xin WANG , Lin CHEN
IPC分类号： C07D471/04 , C07D519/00
CPC分类号： C07D471/04 , C07D519/00
摘要： Provided is a process of synthesizing a substituted pyridine and pyrimidine compound. Particularly, provided is a method for preparing a compound of formula III via a compound of formula II′, wherein the definition of each of groups is as described as the description. Compound with other methods, the method in the present invention has features of high yield and a result product being easier to separate.
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公开(公告)号：US20230099959A1
公开(公告)日：2023-03-30
申请号：US17052853
申请日：2020-07-02
发明人： Bao ZHU , Lin CHEN , Qingqing SUN , Wei ZHANG
IPC分类号： H01L23/48 , H01L21/768
摘要： The present disclosure belongs to the technical field of integrated circuit packaging, and specifically relates to a through silicon via structure for three-dimensional integrated circuit packaging and a manufacturing method thereof. The method of the present disclosure includes the following steps: lifting off a silicon wafer by implanting hydrogen ions into the silicon wafer to obtain a substrate for making a through silicon via; performing double-sided plasma etching on the substrate to form a through silicon via penetrating the substrate; depositing an insulating medium, a copper diffusion barrier layer, and a seed layer; and removing parts of the copper diffusion barrier layer and the seed layer by photolithography and etching processes, leaving only parts of the copper diffusion barrier layer and the seed layer on a sidewall of the through silicon via; forming a sacrificial layer on the upper and lower surfaces of the resulting structure, completely filling in the through silicon via with conductive metal material, and then removing the sacrificial layer, upper and lower surfaces of the conductive metal material respectively protruding from upper and lower surfaces of the insulating medium; and forming a contact pad on a surface of the conductive metal material. The present disclosure can effectively improve production efficiency and lower the cost.
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公开(公告)号：US20230098556A1
公开(公告)日：2023-03-30
申请号：US17052861
申请日：2020-07-02
发明人： Bao ZHU , Lin CHEN , Qingqing SUN , Wei ZHANG
IPC分类号： H01L23/48 , H01L25/065 , H01L23/00 , H10B12/00
摘要： Disclosed is a three-dimensional integrated system for DRAM chips and a fabrication method thereof. A plurality of trench structures are etched on the front and back of a silicon wafer; then, a TSV structure is etched between the two upper and lower trenches opposite to each other for electrical connection; then, DRAM chips are placed in the trenches, and copper-copper bonding is used to make the chips electrically connected to the TSV structure in a vertical direction; finally, redistribution is done to make the chips in a horizontal direction electrically connected. The invention can make full use of silicon materials, and can avoid problems such as warpage and deformation of an interposer. In addition, placing the chips in the trenches will not increase the overall package thickness, while protecting the chips from external impact.
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公开(公告)号：US20230115796A1
公开(公告)日：2023-04-13
申请号：US17052847
申请日：2020-07-02
发明人： Wei ZHANG , Ziyu LIU , Lin CHEN , Qingqing SUN
IPC分类号： H01L23/48 , H01L27/01 , H01L21/768
摘要： The invention pertains to the technical field of semiconductor devices, and specifically relates to a three-dimensional capacitor-inductor based on a high-functional-density through silicon via structure and a manufacturing method. The three-dimensional capacitor-inductor of the present invention includes: a substrate formed with a through silicon via; a three-dimensional capacitor, formed on a sidewall of the through silicon via, and sequentially including a first metal layer, a second insulating layer, and a second metal layer; and a three-dimensional inductor, composed of center-filled metal of the through silicon via and planar thick metal rewiring, wherein a first insulating layer is provided between the sidewall of the through silicon via and the three-dimensional capacitor, and a third insulating layer is provided between the three-dimensional capacitor and the three-dimensional inductor. The invention can effectively increase the values of capacitance and inductance in an integrated system, and at the same time can integrate capacitors and inductors near the chip in three-dimensional integration, and can also improve the functional density of through silicon via in three-dimensional integration and increase the utilization rate of silicon in system integration. Compared with discrete capacitors and inductors on other organic substrates, the integration can be greatly improved.
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公开(公告)号：US20230097450A1
公开(公告)日：2023-03-30
申请号：US17052857
申请日：2020-07-02
发明人： Bao ZHU , Lin CHEN , Qingqing SUN , Wei ZHANG
IPC分类号： H01L23/48 , H01L27/12 , H01L27/092 , H01L21/8238 , H01L21/84 , H01L21/768
摘要： Disclosed is an SOI active interposer for three-dimensional packaging and a fabrication method thereof. An SOI substrate is used as the substrate, and a CMOS inverter is formed on the top silicon of the SOI by using standard integrated circuit manufacturing processes, so that short channel effect and latch-up effect can be suppressed. A via hole structure is etched on the SOI substrate between the PMOS and NMOS transistors of the CMOS inverter, which on the one hand can be used as a conductive channel between the chips in a vertical direction, and on the other hand, can be used as an electrical isolation layer between the PMOS and NMOS transistors.
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7.发明申请公开(公告)号：US20230095639A1
公开(公告)日：2023-03-30
申请号：US17052858
申请日：2020-07-02
发明人： Bao ZHU , Lin CHEN , Qingqing SUN , Wei ZHANG
IPC分类号： G06K19/077 , H01G11/08
摘要： The present disclosure discloses a three-dimensional integration system of an RFID chip and a supercapacitor and a manufacturing method thereof. The three-dimensional integration system of an RFID chip and a supercapacitor includes: a silicon substrate (200); an RFID chip (201) disposed on a front surface of the silicon substrate (200); a supercapacitor disposed on a back surface of the silicon substrate (200) at a position corresponding to the RFID chip (201), but not in contact with the RFID chip (201); through silicon via structures penetrating the silicon substrate (200) and respectively disposed on two sides of the RFID chip (201); wherein the RFID chip (201) has a chip positive electrode (2021) and a chip negative electrode (2022) electrically connected with a capacitor contact positive electrode (2131) and a capacitor contact negative electrode (2132) of the supercapacitor through the through silicon via structures on the two sides respectively; and a packaging substrate (218) electrically connected to the capacitor contact positive electrode (2131) and the capacitor contact negative electrode (2132).
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