公开(公告)号：US20220014506A1

公开(公告)日：2022-01-13

申请号：US17152990

申请日：2021-01-20

申请人： Fuzhou University

发明人： Ximeng LIU ,  Wenzhong GUO ,  Jiayin LI ,  Xiaoyan LI ,  Hongbin ZHUANG

IPC分类号： H04L29/06 ,  G08G1/01

摘要： The present disclosure relates to a realtime urban traffic status monitoring method based on privacy-preserving compressive sensing, including the following steps: step S1: dividing vehicle data under privacy preserving into two parts, and sending the two parts to two different road side units (RSU) for preprocessing; step S2: outsourcing, by the two different RSUs, preprocessed vehicle data to two cloud platforms (CP) respectively, and designing a data encryption execution protocol based on a finally expected operation result and interactive operation between the two CPs, to encrypt the data; and step S3: receiving, by a navigation service provider (NSP), encrypted data from the CPs, decrypting the received encrypted data, and estimating an urban traffic status by using a compressive sensing technology. The present disclosure can remarkably enhance a capability of protecting privacy of vehicle data, ensure rapid and accurate data processing, reduce energy consumed for urban traffic estimation, and shorten required traffic estimation time.

公开(公告)号：US20230401367A1

公开(公告)日：2023-12-14

申请号：US18238562

申请日：2023-08-28

申请人： FUZHOU UNIVERSITY

发明人： Wenzhong GUO ,  Huayang CAI ,  Genggeng LIU ,  Xing HUANG ,  Guolong CHEN

IPC分类号： G06F30/337 ,  G06F17/11

CPC分类号： G06F30/337 ,  G06F17/11 ,  G06F2115/02

摘要： A DRL-based control logic design method for continuous microfluidic biochips is provided. Firstly, an integer linear programming model is for effectively solving multi-channel switching calculation to minimize the number of time slices required by the control logic. Secondly, a control logic synthesis method based on deep reinforcement learning, which uses a double deep Q network and two Boolean logic simplification techniques to find a more effective pattern allocation scheme for the control logic.

公开(公告)号：US20240211671A1

公开(公告)日：2024-06-27

申请号：US18238566

申请日：2023-08-28

申请人： FUZHOU UNIVERSITY

发明人： Genggeng LIU ,  Yuhan ZHU ,  Wenzhong GUO ,  Xing HUANG

IPC分类号： G06F30/392 ,  G06F30/394

CPC分类号： G06F30/392 ,  G06F30/394 ,  G06F2111/06

摘要： A fault-tolerant oriented physical design method for fully programmable valve array biochips is provided. The method comprises the following steps: step S1: constructing component placement constraints, and performing dynamic fault-tolerant placement based on a dynamic constraint placement algorithm of particle swarm optimization and in combination with dynamic fault-tolerant technology, thereby obtaining a fault-tolerant placement scheme without component conflicts; step S2: considering an input sequence of reagents and an A* fault-tolerant routing algorithm based on an optimal input sequence, performing dynamic fault-tolerant routing in combination with the dynamic fault-tolerant technology; and step S3: further processing fluid conflicts in the routing through a routing optimization strategy based on priority and backtracking, so as to obtain a fault-tolerant routing scheme without fluid conflicts.

公开(公告)号：US20220398373A1

公开(公告)日：2022-12-15

申请号：US17776246

申请日：2020-09-30

申请人： FUZHOU UNIVERSITY

发明人： Wenzhong GUO ,  Genggeng LIU ,  Guolong CHEN

IPC分类号： G06F30/398 ,  G06F30/394

摘要： A multi-stage FPGA routing method for optimizing time division multiplexing comprises the following steps: S1: collecting an FPGA set, an FPGA connection pair set, a net set and a net group set; S2: acquiring a routing topology of each net according to the FPGA set, the FPGA connection pair set, the net set and the net group set under the condition where TRs are not assigned; S3: assigning a corresponding TR to each edge of each net according to different delay of each net group; and S4: performing TR reduction and edge validation cyclically, iteratively optimizing net groups with TR being greater than a preset value until iteration end conditions are met, so as to obtain an optimal routing result. The multi-stage FPGA routing method may optimize the delay of inter-chip signals of a multi-FPGA prototype system and guarantee the routability of the multi-FPGA prototype system.