公开(公告)号：US07224060B2

公开(公告)日：2007-05-29

申请号：US10768796

申请日：2004-01-30

申请人： Fan Zhang ,  Kho Liep Chok ,  Tae Jong Lee ,  Xiaomei Bu ,  Meng Luo ,  Chian Yuh Sin ,  Yee Mei Foong ,  Luona Goh ,  Liang Choo Hsia ,  Huey Ming Chong

发明人： Fan Zhang ,  Kho Liep Chok ,  Tae Jong Lee ,  Xiaomei Bu ,  Meng Luo ,  Chian Yuh Sin ,  Yee Mei Foong ,  Luona Goh ,  Liang Choo Hsia ,  Huey Ming Chong

IPC分类号： H01L23/04

CPC分类号： H01L23/585 ,  H01L23/3192 ,  H01L2924/0002 ,  H01L2924/3025 ,  H01L2924/00

摘要： A method of manufacturing an integrated circuit provides a substrate having a semiconductor device, and includes forming an intermetal dielectric layer over the substrate and the semiconductor device. A metal wire is formed above the semiconductor device and in contact therewith and a passivation layer is formed over the intermetal dielectric layer. A bond pad is formed connected to the metal wire. A protective moat, with sidewall passivation layer, is formed through the passivation layer and the intermetal dielectric layer, and is located between the metal wire and an outside edge of the integrated circuit.

摘要翻译： 制造集成电路的方法提供了具有半导体器件的衬底，并且包括在衬底和半导体器件上形成金属间电介质层。 金属线形成在半导体器件的上方并与之接触，并且在金属间电介质层之上形成钝化层。 形成与金属线连接的接合焊盘。 通过钝化层和金属间电介质层形成具有侧壁钝化层的保护护套，并且位于金属线和集成电路的外边缘之间。

公开(公告)号：US20050167824A1

公开(公告)日：2005-08-04

申请号：US10768796

申请日：2004-01-30

申请人： Fan Zhang ,  Kho Chok ,  Tae Lee ,  Xiaomei Bu ,  Meng Luo ,  Chian Sin ,  Yee Foong ,  Luona Goh ,  Liang Hsia ,  Huey Chong

发明人： Fan Zhang ,  Kho Chok ,  Tae Lee ,  Xiaomei Bu ,  Meng Luo ,  Chian Sin ,  Yee Foong ,  Luona Goh ,  Liang Hsia ,  Huey Chong

IPC分类号： H01L23/52 ,  H01L21/3205 ,  H01L21/822 ,  H01L23/04 ,  H01L23/31 ,  H01L23/58 ,  H01L27/04

CPC分类号： H01L23/585 ,  H01L23/3192 ,  H01L2924/0002 ,  H01L2924/3025 ,  H01L2924/00

摘要： A method of manufacturing an integrated circuit provides a substrate having a semiconductor device, and includes forming an intermetal dielectric layer over the substrate and the semiconductor device. A metal wire is formed above the semiconductor device and in contact therewith and a passivation layer is formed over the intermetal dielectric layer. A bond pad is formed connected to the metal wire. A protective moat, with sidewall passivation layer, is formed through the passivation layer and the intermetal dielectric layer, and is located between the metal wire and an outside edge of the integrated circuit.

摘要翻译： 制造集成电路的方法提供了具有半导体器件的衬底，并且包括在衬底和半导体器件上形成金属间电介质层。 金属线形成在半导体器件的上方并与之接触，并且在金属间电介质层之上形成钝化层。 形成与金属线连接的接合焊盘。 通过钝化层和金属间电介质层形成具有侧壁钝化层的保护护套，并且位于金属线和集成电路的外边缘之间。