公开(公告)号：US09385733B2

公开(公告)日：2016-07-05

申请号：US14527779

申请日：2014-10-30

Applicant: Faraday Technology Corp.

Inventor： Chia-Liang Lai ,  Song-Rong Han ,  Jung-Yu Chang ,  Wei-Ming Lin

IPC: H03L7/197 ,  H03K23/68

CPC classification number: H03L7/1976 ,  H03K21/023 ,  H03K23/68 ,  H03L7/1974

Abstract: A clock generating apparatus and a fractional frequency divider thereof are provided. The fractional frequency divider includes a frequency divider (FD), a plurality of samplers, a selector and a control circuit. An input terminal of the FD is coupled to an output terminal of a multi-phase-frequency generating circuit. Input terminals of the samplers are coupled to an output terminal of the FD. Trigger terminals of the samplers receive the sampling clock signals. The input terminals of the selector are coupled to output terminals of the samplers. An output terminal of the selector is coupled to a feedback terminal of the multi-phase-frequency generating circuit. The control circuit provides a fraction code to a control terminal of the selector, so as to control the selector for selectively coupling the output terminal of one of the samplers to the feedback terminal of the multi-phase-frequency generating circuit.

Abstract translation: 提供时钟发生装置及其分数分频器。 分数分频器包括分频器（FD），多个采样器，选择器和控制电路。 FD的输入端耦合到多相频率发生电路的输出端。 采样器的输入端耦合到FD的输出端。 采样器的触发端接收采样时钟信号。 选择器的输入端耦合到采样器的输出端。 选择器的输出端耦合到多相频率发生电路的反馈端。 控制电路向选择器的控制端提供分数代码，以便控制选择器选择性地将一个采样器的输出端耦合到多相频率发生电路的反馈端。