公开(公告)号：US11418003B2

公开(公告)日：2022-08-16

申请号：US16533714

申请日：2019-08-06

Applicant: FINISAR CORPORATION

Inventor： Jianwei Mu ,  Frank Lei Ding ,  Tao Wu ,  Hongyu Deng ,  Maziar Amirkiai

IPC: H01S5/02325 ,  H01L23/498 ,  H01S5/024 ,  H01L23/34 ,  H01L21/48 ,  H01S5/0233 ,  H01S5/0235

Abstract: A chip may include a first substantially planar isolation layer with a first surface and a second surface opposite the first surface. The chip may include a first substantially planar conduction layer with a first surface positioned adjacent to the second surface of the first isolation layer and a second surface opposite the first surface. The chip may include a second substantially planar isolation layer with a first surface positioned adjacent to the second surface of the first conduction layer and a second surface opposite the first surface. The chip may include a second conduction layer etched on the second surface of the second isolation layer. The second conduction layer may include an anode trace, a cathode trace, and an optical transmitter positioned on the cathode trace. The chip may include one or more vias through the second isolation layer electrically coupling the anode trace with the first conduction layer.

公开(公告)号：US10816739B2

公开(公告)日：2020-10-27

申请号：US16600194

申请日：2019-10-11

Applicant: Finisar Corporation

Inventor： Frank Lei Ding ,  Maziar Amirkiai ,  Jianwei Mu ,  Hongyu Deng ,  Tao Wu

IPC: G02B6/42

Abstract: A resistance weldable cover for an OSA may include multiple walls, one or more supports, and an opening disposed in one of the walls. The walls may define an interior cavity within the walls. The one or more supports may extend from one or more of the walls. Each of the one or more supports may be weldable to a heat sink stiffener. The opening may be sized and shaped to receive at least a portion of a barrel such that optical signals are transmittable between the interior cavity and the barrel.

公开(公告)号：US20200116961A1

公开(公告)日：2020-04-16

申请号：US16600194

申请日：2019-10-11

Applicant: Finisar Corporation

Inventor： Frank Lei Ding ,  Maziar Amirkiai ,  Jianwei Mu ,  Hongyu Deng ,  Tao Wu

IPC: G02B6/42

Abstract: A resistance weldable cover for an OSA may include multiple walls, one or more supports, and an opening disposed in one of the walls. The walls may define an interior cavity within the walls. The one or more supports may extend from one or more of the walls. Each of the one or more supports may be weldable to a heat sink stiffener. The opening may be sized and shaped to receive at least a portion of a barrel such that optical signals are transmittable between the interior cavity and the barrel.

公开(公告)号：US10952312B2

公开(公告)日：2021-03-16

申请号：US16178507

申请日：2018-11-01

Applicant: Finisar Corporation

Inventor： Jianwei Mu ,  Hongyu Deng

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/18 ,  H01P3/02 ,  H01P5/02 ,  H01P3/00

Abstract: A communication module may include a communication ground layer. The communication module may also include a circuit board. The circuit board may be located proximate the communication ground layer. The circuit board may include a stitch layer. The stitch layer may be electrically coupled to the communication ground layer via a plurality of stitch layer vias. Additionally, the communication module may include multiple ground vias. The ground vias may be electrically coupled to a portion of the circuit board and to the communication ground layer.

公开(公告)号：US10374386B1

公开(公告)日：2019-08-06

申请号：US16003074

申请日：2018-06-07

Applicant: Finisar Corporation

Inventor： Jianwei Mu ,  Frank Lei Ding ,  Tao Wu ,  Hongyu Deng ,  Maziar Amirkiai

IPC: H01S5/022 ,  H01L23/498 ,  H01S5/024 ,  H01L23/34 ,  H01L21/48

Abstract: A chip may include a first substantially planar isolation layer with a first surface and a second surface opposite the first surface. The chip may include a first substantially planar conduction layer with a first surface positioned adjacent to the second surface of the first isolation layer and a second surface opposite the first surface. The chip may include a second substantially planar isolation layer with a first surface positioned adjacent to the second surface of the first conduction layer and a second surface opposite the first surface. The chip may include a second conduction layer etched on the second surface of the second isolation layer. The second conduction layer may include an anode trace, a cathode trace, and an optical transmitter positioned on the cathode trace. The chip may include one or more vias through the second isolation layer electrically coupling the anode trace with the first conduction layer.

公开(公告)号：US20190132941A1

公开(公告)日：2019-05-02

申请号：US16178507

申请日：2018-11-01

Applicant: Finisar Corporation

Inventor： Jianwei Mu ,  Hongyu Deng

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/18

Abstract: A communication module may include a communication ground layer. The communication module may also include a circuit board. The circuit board may be located proximate the communication ground layer. The circuit board may include a stitch layer. The stitch layer may be electrically coupled to the communication ground layer via a plurality of stitch layer vias. Additionally, the communication module may include multiple ground vias. The ground vias may be electrically coupled to a portion of the circuit board and to the communication ground layer.