公开(公告)号：US20100138588A1

公开(公告)日：2010-06-03

申请号：US12326811

申请日：2008-12-02

申请人： Fong Long Lin ,  Je-Hurn Shieh

发明人： Fong Long Lin ,  Je-Hurn Shieh

IPC分类号： G06F12/02 ,  G06F12/00

CPC分类号： G11C16/3418

摘要： A controller operates a NAND non-volatile memory device which has an array of non-volatile memory cells. The array of non-volatile memory cells is susceptible to suffering loss of data stored in one or more memory cells of the array. The controller interfaces with a host device and receives from the host device a time-stamp signal. The controller comprises a processor, and a memory having program code stored therein for execution by the processor. The program code is configured to receive by the controller the time stamp signal from the host device; to compare the received time stamp signal with a stored signal wherein the stored signal is a time stamp signal received earlier in time by the controller from the host device; and to determine when to perform a data retention and refresh operation for data stored in the memory array based upon the comparing step.

摘要翻译： 控制器操作具有非易失性存储器单元阵列的NAND非易失性存储器件。 非易失性存储器单元的阵列容易受到存储在阵列的一个或多个存储器单元中的数据的损失。 控制器与主机设备接口，并从主机设备接收时间戳信号。 控制器包括处理器和存储有程序代码的存储器，用于由处理器执行。 程序代码被配置为由控制器接收来自主机设备的时间戳信号; 将所接收的时间戳信号与存储的信号进行比较，其中所存储的信号是控制器从主机设备及时接收到的时间戳信号; 并且基于比较步骤确定何时对存储在存储器阵列中的数据执行数据保留和刷新操作。

公开(公告)号：US06333959B1

公开(公告)日：2001-12-25

申请号：US09557521

申请日：2000-04-25

申请人： Steven Lai ,  Je-Hurn Shieh

发明人： Steven Lai ,  Je-Hurn Shieh

IPC分类号： G11C1900

CPC分类号： H03L7/0814 ,  G11C19/00 ,  G11C19/28 ,  H03K5/135

摘要： A simplified bi-directional shift register and a single-latch circuit for implementing the bi-directional shift register thereof which obviates the use of a conventional dual-latch (i.e., master/slave) configuration in the bi-directional shift register design is described. The single-latch circuit includes an input circuit portion and a latching circuit portion. The input circuit portion receives input signals including the output data from previous and next single-latch circuits in the shift register and right shift and left shift control signals. Dependent on the input signals, the input circuit portion drives an input node coupled to the latching circuit portion with a data value to be shifted which corresponds to data from one of the previous and next single-latch circuits. The latching circuit portion includes a tri-state inverter which is responsive to the system clock signal such that when the clock signal transitions to a given state, the data value to be shifted is latched to the output of the single-latch circuit wherein the shift operation is performed. A delay lock loop circuit implemented with a bi-directional shift register designed with the single-latch circuit has reduced size and minimized noise due to the simplicity of the single-latch circuit.

摘要翻译： 描述了用于实现其双向移位寄存器的简化的双向移位寄存器和单锁存电路，其消除了双向移位寄存器设计中常规双锁存器（即，主/从））配置的使用 。 单锁存电路包括输入电路部分和锁存电路部分。 输入电路部分接收包括来自移位寄存器中的前一个和下一个单个锁存电路的输出数据的输入信号，以及右移位和左移位控制信号。 根据输入信号，输入电路部分驱动耦合到锁存电路部分的输入节点，其中要移位的数据值对应于来自前一个和下一个单锁存电路之一的数据。 锁存电路部分包括响应于系统时钟信号的三态反相器，使得当时钟信号转变到给定状态时，要移位的数据值被锁存到单锁存电路的输出，其中移位 执行操作。 使用单锁存电路设计的双向移位寄存器实现的延迟锁定环电路由于单锁存电路的简单性而减小了尺寸并降低了噪声。

公开(公告)号：US06323705B1

公开(公告)日：2001-11-27

申请号：US09559020

申请日：2000-04-25

申请人： Je-Hurn Shieh ,  Steven Lai

发明人： Je-Hurn Shieh ,  Steven Lai

IPC分类号： H03L706

CPC分类号： G11C7/222 ,  G11C7/22 ,  H03L7/0814 ,  H03L7/089 ,  H03L7/10

摘要： A double data rate (DDR) synchronous dynamic RAM (SDRAM) includes delay lock loop circuitry which is designed so as to significantly reduce the locking period associated with achieving the lock state of the delay lock loop. The delay lock loop circuit includes a first adjustable delay unit circuit for delaying the external clock so as to provide the DDR operation and includes a feedback loop having a shift register controlled by a phase detector which is used to set an optimum delay value. The delay value is then used to control the first delay unit circuit and determine the amount of delay time it provides. The delay lock loop further includes a second delay unit circuit which is initially enabled by the rising edge of the first clock cycle of an internal feedback clock signal and then is disabled by the rising edge of the second clock cycle of the external clock signal such that a digital value in close range to the optimum lock state delay value is established on the output of the second delay unit circuit by the second cycle of the external clock signal. This digital value is used to pre-set the shift register which, in turn, is used to control the first delay unit. As a result, the period of time required to achieve a lock state within the delay lock loop circuit and stand-by current consumption due to the DLL circuit are significantly reduced.

摘要翻译： 双数据速率（DDR）同步动态RAM（SDRAM）包括延迟锁定环路电路，其被设计为显着减少与实现延迟锁定环路的锁定状态相关联的锁定时段。 延迟锁定环路电路包括用于延迟外部时钟以提供DDR操作的第一可调节延迟单元电路，并且包括具有由用于设置最佳延迟值的相位检测器控制的移位寄存器的反馈环路。 然后延迟值用于控制第一延迟单元电路并确定其提供的延迟时间量。 延迟锁定环还包括第二延迟单元电路，其最初由内部反馈时钟信号的第一时钟周期的上升沿使能，然后被外部时钟信号的第二时钟周期的上升沿禁止，使得 通过外部时钟信号的第二周期在第二延迟单元电路的输出上建立接近最佳锁定状态延迟值的数字值。 该数字值用于预设移位寄存器，而移位寄存器又用于控制第一延迟单元。 结果，在延迟锁定环路电路中实现锁定状态所需的时间段和由于DLL电路引起的待机电流消耗显着减少。

公开(公告)号：US5903171A

公开(公告)日：1999-05-11

申请号：US865076

申请日：1997-05-29

申请人： Je-Hurn Shieh

发明人： Je-Hurn Shieh

IPC分类号： G11C7/06

CPC分类号： G11C7/065

摘要： A sense amplifier having an ingegrated latch with level shift is disclosed, in which a pair of cross-connected inverters are connected between the outputs of the sense amplifier to provide a single stage amplifier. The sense amplifier performs level shift, sense amplifier and latching functions within a single circuit, thus reducing layout area and simplifying chip design while at the same time providing full swing complementary outputs. In addition, the sense amplifier is turned on for only a portion of the cycle to enable the data to be latched, with virtually no constant current comsumption in the circuit for holding the data, thereby reducing power consumption. Alternative embodiments are disclosed using conventional and tri-state latches.

摘要翻译： 公开了具有电平移位的嵌入式锁存器的读出放大器，其中一对交叉连接的反相器连接在读出放大器的输出端之间以提供单级放大器。 读出放大器在单个电路内执行电平移位，读出放大器和锁存功能，从而减少布局面积并简化芯片设计，同时提供全摆幅互补输出。 此外，只有一部分周期的读出放大器导通才能使数据被锁存，实际上电路中没有恒定的电流消耗用于保存数据，从而降低功耗。 使用常规和三态锁存器公开了替代实施例。