公开(公告)号：US20130185525A1

公开(公告)日：2013-07-18

申请号：US13723798

申请日：2012-12-21

Applicant: Foundation of Soongsil University-Industry Cooperation

Inventor： Chan-Ho LEE

IPC: G06F12/00

CPC classification number: G06F12/00 ,  G06F13/1621 ,  G06F13/1631 ,  Y02D10/14

Abstract: Disclosed herein are a semiconductor chip for adaptively processing a plurality of commands to request memory access, and a method of controlling memory. The semiconductor chip includes a storage unit ad a control unit. The storage unit stores a memory access request to be currently processed and a plurality of memory access requests received before the memory access request to be currently processed in received order. The control unit processes the memory access request to be currently processed and the plurality of memory access requests received before the memory access request to be currently processed, which have been stored in the storage unit, in received order, except that memory access requests attempting to access the same bank and the same row are successively processed.

Abstract translation: 这里公开了一种用于自适应地处理多个命令以请求存储器访问的半导体芯片，以及一种控制存储器的方法。 半导体芯片包括存储单元和控制单元。 存储单元存储当前处理的存储器访问请求和在接收到的顺序当前处理的存储器访问请求之前接收的多个存储器访问请求。 控制单元以接收的顺序处理当前处理的存储器访问请求和在存储在存储单元中的当前处理的存储器访问请求之前接收到的多个存储器访问请求，除了存储器访问请求尝试 连续处理访问同一行和同一行。

公开(公告)号：US20130286762A1

公开(公告)日：2013-10-31

申请号：US13735171

申请日：2013-01-07

Applicant: Foundation of Soongsil University-Industry Cooperation

Inventor： Chan-Ho LEE

IPC: G11C8/12

CPC classification number: G11C8/12 ,  G11C8/06 ,  G11C8/08 ,  G11C11/408

Abstract: Provided are a memory control apparatus and a memory control method. In the memory control apparatus and memory control method, data are distributively stored in a plurality of banks in sequence, and the corresponding data are written to or read from the memory, based on row address information obtained by exchanging a portion of row information and bank information with each other. According to the invention, if a new row begins when the host or the processor accesses the memory, a host or a processor accesses another bank, and thus the block data can be read or written without a waiting cycle. In addition, the memory control apparatus and the memory control method can be implemented with low complexity available through simple address conversion in the memory control apparatus.

Abstract translation: 提供了一种存储器控制装置和存储器控制方法。 在存储器控制装置和存储器控制方法中，数据按顺序分布存储在多个存储体中，并且根据通过交换行信息和存储体的一部分获得的行地址信息将对应的数据写入存储器或从存储器读取 相互信息。 根据本发明，如果在主机或处理器访问存储器时新的行开始，则主机或处​​理器访问另一个存储体，因此可以在没有等待周期的情况下读取或写入块数据。 此外，存储器控制装置和存储器控制方法可以通过存储器控制装置中的简单地址转换而具有低复杂度来实现。