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    Fabrication of active areas of different natures directly onto an insulator: application to the single or double gate MOS transistor
    1.
    发明授权
    Fabrication of active areas of different natures directly onto an insulator: application to the single or double gate MOS transistor 有权
    将不同性质的有源区域直接制造到绝缘体上：应用于单栅极或双栅极MOS晶体管

    公开(公告)号：US07820523B2

    公开(公告)日：2010-10-26

    申请号：US11579037

    申请日：2004-06-25

    申请人： François Andrieu ,  Thomas Ernst ,  Simon Deleonibus

    发明人： François Andrieu ,  Thomas Ernst ,  Simon Deleonibus

    IPC分类号： H01L21/30

    CPC分类号： H01L27/1203 ,  H01L21/76275 ,  H01L21/84 ,  H01L29/045 ,  H01L29/78648 ,  H01L29/78684 ,  Y10S117/915

    摘要： The invention concerns a micro-electronic device comprising a substrate, a first insulating zone and a second insulating zone laying on said substrate, a first active zone comprising at least one layer made of a first semi-conductor crystalline material, resting on said first insulating zone which insulates it from the substrate, at least one second active zone comprising at least one layer in a second semi-conductor crystalline material, laying on said second insulating zone which insulates it from the substrate, said first semi-conductor crystalline material having a different composition from that of the second semi-conductor crystalline material and/or different crystalline orientation from that of the second semi-conductor crystalline material and/or mechanical strains from that of the second semi-conductor crystalline material.

    摘要翻译： 本发明涉及一种包括衬底，第一绝缘区和布置在所述衬底上的第二绝缘区的微电子器件，第一有源区包括由第一半导体晶体材料制成的至少一层，位于所述第一绝缘层上 所述第一半导体结晶材料具有与基底绝缘的区域，至少一个第二活性区域，包括在第二半导体结晶材料中的至少一个层，铺设在所述第二绝缘区域上， 与第二半导体结晶材料不同的组成和/或与第二半导体结晶材料不同的晶体取向和/或来自第二半导体晶体材料的机械应变。

    Method of adjusting the threshold voltage of a transistor by a buried trapping layer
    2.
    发明授权
    Method of adjusting the threshold voltage of a transistor by a buried trapping layer 有权
    通过埋置捕获层调节晶体管的阈值电压的方法

    公开(公告)号：US08809964B2

    公开(公告)日：2014-08-19

    申请号：US12865549

    申请日：2009-02-11

    申请人： François Andrieu ,  Emmanuel Augendre ,  Laurent Clavelier ,  Marek Kostrzewa

    发明人： François Andrieu ,  Emmanuel Augendre ,  Laurent Clavelier ,  Marek Kostrzewa

    IPC分类号： H01L21/336 ,  H01L29/792

    CPC分类号： H01L29/42348 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/792

    摘要： An electronic subassembly and associated method for the production of an electronic subassembly include a semiconductor layer bearing at least a first transistor having an adjustable threshold voltage is joined to an insulator layer and in which a first trapping zone is formed at a predetermined first depth. The first trapping zone extends at least beneath a channel of the first transistor and includes traps of greater density than the density of traps outside the first trapping zone, in such a way that the semiconductor layer and the first trapping zone are capacitively coupled. The useful information from the first transistor includes the charge transport within this transistor. A second trapping zone can be formed that extends at least beneath a channel of a second transistor that is formed by a second implantation with an energy and/or a dose and/or atoms that differ from those used to form the first trapping zone.

    摘要翻译： 一种用于生产电子组件的电子组件和相关方法，包括至少具有可调阈值电压的第一晶体管的半导体层被连接到绝缘体层，并且其中在预定的第一深度形成第一捕集区。 第一捕获区至少在第一晶体管的沟道下方延伸，并且包括具有比第一捕获区外的阱的密度更高密度的陷阱，使得半导体层和第一捕获区电容耦合。 来自第一晶体管的有用信息包括该晶体管内的电荷传输。 可以形成第二捕获区，其至少在通过第二注入形成的第二晶体管的沟道下方延伸，所述第二晶体管具有不同于用于形成第一捕获区的能量和/或剂量和/或原子的能量和/或原子。