Method for activating double metal cyanide catalysts for producing polyether polyols
    1.
    发明授权
    Method for activating double metal cyanide catalysts for producing polyether polyols 有权
    活化用于制备聚醚多元醇的双金属氰化物催化剂的方法

    公开(公告)号:US09249259B2

    公开(公告)日:2016-02-02

    申请号:US14232015

    申请日:2012-07-17

    摘要: The present invention relates to a process for the activation of double metal cyanide (DMC) catalysts and to a process for the preparation of polyethercarbonate polyols from one or more H-functional starter compounds, one or more alkylene oxides and carbon dioxide in the presence of a double metal cyanide catalyst, characterized in that (α) (α1) the DMC catalyst and one or more H-functional starter compounds are placed in a reactor, (α2) an inert gas, an inert gas/carbon dioxide mixture or carbon dioxide is passed through the reactor at a temperature of 50 to 200° C. and at the same time a reduced pressure (absolute) of 10 mbar to 800 mbar is established in the reactor by removal of the inert gas or carbon dioxide, (β) under an atmosphere of inert gas/carbon dioxide mixture or under a pure carbon dioxide atmosphere, alkylene oxide is added to the mixture from step (α) at temperatures of 50 to 200° C., and (γ) one or more alkylene oxides and carbon dioxide are metered into the mixture resulting from step (β).

    摘要翻译: 本发明涉及一种活化双金属氰化物(DMC)催化剂的方法,以及一种由一种或多种H官能起始化合物,一种或多种环氧烷和二氧化碳在存在下制备聚醚碳酸酯多元醇的方法 一种双金属氰化物催化剂,其特征在于将(α)(α1)DMC催化剂和一种或多种H官能起始化合物置于反应器中,(α2)惰性气体,惰性气体/二氧化碳混合物或二氧化碳 在50至200℃的温度下通过反应器,同时通过除去惰性气体或二氧化碳,在反应器中建立10毫巴至800毫巴的减压(绝对)(绝对)。 )在惰性气体/二氧化碳混合物的气氛下或在纯二氧化碳气氛下,在步骤(α)的混合物中,在50〜200℃的温度下加入环氧烷,(γ)一种或多种环氧烷烃 并将二氧化碳计量加入 由(步骤(bgr))产生的混合物。

    Multilevel memory device
    2.
    发明授权
    Multilevel memory device 有权
    多级存储器件

    公开(公告)号:US09019760B2

    公开(公告)日:2015-04-28

    申请号:US13304531

    申请日:2011-11-25

    摘要: A memory device is provided, including a back gate including a first portion of electrically conductive material, a first portion of dielectric material arranged on the back gate, a semiconductor nanobeam arranged on the first portion of dielectric material, a second portion of dielectric material covering the semiconductor nanobeam, a portion of material configured to receive electrons and holes, and configured to store electrical charges and covering the second portion of dielectric material, a third portion of dielectric material covering the portion of material configured to perform storage of electrical charges, and a front gate including a second portion of electrically conductive material covering the third portion of dielectric material.

    摘要翻译: 提供了一种存储器件,包括一个包括导电材料的第一部分的背栅,布置在背栅上的介质材料的第一部分,布置在电介质材料第一部分上的半导体纳米结构体,覆盖电介质材料的第二部分 半导体纳米结构体,被配置为接收电子和空穴并被配置为存储电荷并覆盖电介质材料的第二部分的材料的一部分,覆盖被配置为执行电荷存储的材料部分的介电材料的第三部分,以及 前门,其包括覆盖电介质材料的第三部分的导电材料的第二部分。

    SRAM memory cell provided with transistors having a vertical multichannel structure
    5.
    发明授权
    SRAM memory cell provided with transistors having a vertical multichannel structure 有权
    具有垂直多通道结构的晶体管的SRAM存储单元

    公开(公告)号:US08502318B2

    公开(公告)日:2013-08-06

    申请号:US12740907

    申请日:2008-11-07

    IPC分类号: H01L29/66

    摘要: A microelectronic device including, on a substrate, at least one element such as a SRAM memory cell; one or more first transistor(s), respectively including a number k of channels (k≧1) parallel in a direction forming a non-zero angle with the main plane of the substrate, and one or more second transistor(s), respectively including a number m of channels, such that m>k, parallel in a direction forming a non-zero angle, or an orthogonal direction, with the main plane of the substrate.

    摘要翻译: 一种微电子器件,在衬底上包括诸如SRAM存储单元的至少一个元件; 分别包括在与衬底的主平面形成非零角度的方向上平行的数k个通道(k> = 1)的一个或多个第一晶体管和一个或多个第二晶体管, 分别包括与形成非零角度的方向或正交方向平行的m> k个通道的数量m与基板的主平面。

    Method of manufacturing nanowires parallel to the supporting substrate
    6.
    发明授权
    Method of manufacturing nanowires parallel to the supporting substrate 有权
    制造平行于支撑衬底的纳米线的方法

    公开(公告)号:US08252636B2

    公开(公告)日:2012-08-28

    申请号:US12267431

    申请日:2008-11-07

    摘要: A method of manufacturing at least one nanowire, the nanowire being parallel to its supporting substrate, the method including the formation on the supporting substrate of a structure comprising a bar and two regions, a first end of the bar being secured to one of the two regions and a second end of the bar being secured to the other region, the width of the bar being less than the width of the regions, the subjection of the bar to an annealing under gaseous atmosphere in order to transform the bar into a nanowire, the annealing being carried out under conditions allowing control of the sizing of the neck produced during the formation of the nanowire.

    摘要翻译: 一种制造至少一个纳米线的方法,所述纳米线平行于其支撑衬底,所述方法包括在支撑衬底上形成包括棒和两个区域的结构,所述棒的第一端固定到两个之一 区域,并且杆的第二端固定到另一区域,杆的宽度小于区域的宽度,在棒状气体气氛下退火以便将棒转变成纳米线, 退火在允许控制在纳米线形成期间产生的颈部上浆的条件下进行。

    PRODUCTION OF A TRANSISTOR GATE ON A MULTIBRANCH CHANNEL STRUCTURE AND MEANS FOR ISOLATING THIS GATE FROM THE SOURCE AND DRAIN REGIONS
    8.
    发明申请
    PRODUCTION OF A TRANSISTOR GATE ON A MULTIBRANCH CHANNEL STRUCTURE AND MEANS FOR ISOLATING THIS GATE FROM THE SOURCE AND DRAIN REGIONS 有权
    生产多晶闸道结构的晶体闸门和从源头和排水区隔离这一门槛的手段

    公开(公告)号:US20110281412A1

    公开(公告)日:2011-11-17

    申请号:US13190125

    申请日:2011-07-25

    IPC分类号: H01L21/336

    摘要: A method for fabricating a microelectronic device comprising: a support, an etched stack of thin layers comprising: at least one first block and at least one second block resting on the support, in which at least one drain region and at least one source region, respectively, are capable of being formed, several semiconductor bars connecting a first zone of the first block and another zone of the second block, and able to form a multi-branch transistor channel, or several transistor channels, the device also comprising: a gate surrounding said bars and located between said first block and said second block, the gate being in contact with a first and a second insulating spacer in contact with at least one sidewall of the first block and with at least one sidewall of the second block, respectively, and at least partially separated from the first block and the second block, via said insulating spacers.

    摘要翻译: 一种用于制造微电子器件的方法,包括:支撑体,蚀刻的薄层叠层,包括:至少一个第一块和搁置在所述支撑上的至少一个第二块,其中至少一个漏极区和至少一个源极区, 能够形成多个半导体条,连接第一块的第一区和第二块的另一区,并且能够形成多分支晶体管沟道或多个晶体管沟道,该器件还包括:栅极 围绕所述杆并且位于所述第一块和所述第二块之间,所述栅极与分别与所述第一块的至少一个侧壁和所述第二块的至少一个侧壁接触的第一和第二绝缘间隔件接触; 并且经由所述绝缘间隔件至少部分地与第一块和第二块分离。

    Methods and systems for monitoring operation of a wind turbine
    9.
    发明授权
    Methods and systems for monitoring operation of a wind turbine 有权
    用于监测风力发电机运行的方法和系统

    公开(公告)号:US08021112B2

    公开(公告)日:2011-09-20

    申请号:US12826244

    申请日:2010-06-29

    IPC分类号: F03D7/04

    摘要: A method for monitoring wear of a blade pitch brake within a rotor blade pitch control system of a wind turbine is described. The rotor blade pitch control system includes a blade pitch actuator. The method includes engaging the blade pitch brake and measuring a blade pitch displacement while the blade pitch brake is engaged. The method further includes determining a brake wear level based on the measured blade pitch displacement while the blade pitch brake is engaged, and generating a brake wear level output signal corresponding to the brake wear level.

    摘要翻译: 描述了一种用于监测风力涡轮机的转子叶片桨距控制系统内的叶片桨距制动器的磨损的方法。 转子叶片桨距控制系统包括桨叶桨距致动器。 该方法包括在叶片桨距制动器接合时接合叶片桨距制动器并测量叶片桨距位移。 所述方法还包括:当所述叶片桨距制动器接合时,基于所测量的叶片间距位移来确定制动磨损水平,并且产生对应于所述制动磨损水平的制动磨损水平输出信号。