公开(公告)号：US08809964B2

公开(公告)日：2014-08-19

申请号：US12865549

申请日：2009-02-11

申请人： François Andrieu ,  Emmanuel Augendre ,  Laurent Clavelier ,  Marek Kostrzewa

发明人： François Andrieu ,  Emmanuel Augendre ,  Laurent Clavelier ,  Marek Kostrzewa

IPC分类号： H01L21/336 ,  H01L29/792

CPC分类号： H01L29/42348 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/792

摘要： An electronic subassembly and associated method for the production of an electronic subassembly include a semiconductor layer bearing at least a first transistor having an adjustable threshold voltage is joined to an insulator layer and in which a first trapping zone is formed at a predetermined first depth. The first trapping zone extends at least beneath a channel of the first transistor and includes traps of greater density than the density of traps outside the first trapping zone, in such a way that the semiconductor layer and the first trapping zone are capacitively coupled. The useful information from the first transistor includes the charge transport within this transistor. A second trapping zone can be formed that extends at least beneath a channel of a second transistor that is formed by a second implantation with an energy and/or a dose and/or atoms that differ from those used to form the first trapping zone.

摘要翻译： 一种用于生产电子组件的电子组件和相关方法，包括至少具有可调阈值电压的第一晶体管的半导体层被连接到绝缘体层，并且其中在预定的第一深度形成第一捕集区。 第一捕获区至少在第一晶体管的沟道下方延伸，并且包括具有比第一捕获区外的阱的密度更高密度的陷阱，使得半导体层和第一捕获区电容耦合。 来自第一晶体管的有用信息包括该晶体管内的电荷传输。 可以形成第二捕获区，其至少在通过第二注入形成的第二晶体管的沟道下方延伸，所述第二晶体管具有不同于用于形成第一捕获区的能量和/或剂量和/或原子的能量和/或原子。

公开(公告)号：US20110001184A1

公开(公告)日：2011-01-06

申请号：US12865549

申请日：2009-02-11

申请人： Francois Andrieu ,  Emmanuel Augendre ,  Laurent Clavelier ,  Marek Kostrzewa

发明人： Francois Andrieu ,  Emmanuel Augendre ,  Laurent Clavelier ,  Marek Kostrzewa

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L29/42348 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/792

摘要： An electronic subassembly and associated method for the production of an electronic subassembly include a semiconductor layer bearing at least a first transistor having an adjustable threshold voltage is joined to an insulator layer and a in which a first trapping zone is formed at a predetermined first depth. The first trapping zone extends at least beneath a channel of the first transistor and includes traps of greater density than the density of traps outside the first trapping zone, in such a way that the semiconductor layer and the first trapping zone are capacitively coupled. The useful information from the first transistor includes the charge transport within this transistor. A second trapping zone can be formed that extends at least beneath a channel of a second transistor that is formed by a second implantation with an energy and/or a dose and/or atoms that differ from those used to form the first trapping zone.

摘要翻译： 一种用于生产电子组件的电子组件和相关联的方法，包括至少具有可调阈值电压的第一晶体管的半导体层被连接到绝缘体层，其中在预定的第一深度处形成第一捕集区。 第一捕获区至少在第一晶体管的沟道下方延伸，并且包括具有比第一捕获区外的阱的密度更高密度的陷阱，使得半导体层和第一捕获区电容耦合。 来自第一晶体管的有用信息包括该晶体管内的电荷传输。 可以形成第二捕获区，其至少在通过第二注入形成的第二晶体管的沟道下方延伸，所述第二晶体管具有不同于用于形成第一捕获区的能量和/或剂量和/或原子的能量和/或原子。

公开(公告)号：US07879690B2

公开(公告)日：2011-02-01

申请号：US12413130

申请日：2009-03-27

申请人： Emmanuel Augendre ,  Thomas Ernst ,  Marek Kostrzewa ,  Hubert Moriceau

发明人： Emmanuel Augendre ,  Thomas Ernst ,  Marek Kostrzewa ,  Hubert Moriceau

IPC分类号： H01L21/30 ,  H01L21/46

CPC分类号： H01L21/76254

摘要： A microstructure of the semiconductor on insulator type with different patterns is produced by forming a stacked uniform structure including a plate forming a substrate, a continuous insulative layer and a semiconductor layer. The continuous insulative layer is a stack of at least three elementary layers, including a bottom elementary layer, at least one intermediate elementary layer, and a top elementary layer overlying the semiconductor layer, where at least one of the bottom elementary layer and the top elementary layer being of an insulative material. In the stacked uniform structure, at least two patterns are differentiated by modifying at least one of the elementary layers in one of the patterns so that the elementary layer has a significantly different physical or chemical property between the two patterns, where at least one of the bottom and top elementary layer is an insulative material that remains unchanged.

摘要翻译： 通过形成包括形成衬底的板，连续绝缘层和半导体层的层叠均匀结构，来产生具有不同图案的绝缘体半导体型微结构。 连续绝缘层是至少三个基本层的堆叠，包括底部基本层，至少一个中间基本层和覆盖半导体层的顶部基本层，其中底部基本层和顶部基本层中的至少一个 层是绝缘材料。 在层叠的均匀结构中，通过修改其中一个图案中的至少一个基本层来区分至少两个图案，使得元件层在两个图案之间具有显着不同的物理或化学性质，其中至少一个 底部和顶部基本层是保持不变的绝缘材料。

公开(公告)号：US20090246946A1

公开(公告)日：2009-10-01

申请号：US12413130

申请日：2009-03-27

申请人： Emmanuel Augendre ,  Thomas Ernst ,  Marek Kostrzewa ,  Hubert Moriceau

发明人： Emmanuel Augendre ,  Thomas Ernst ,  Marek Kostrzewa ,  Hubert Moriceau

IPC分类号： H01L21/762

CPC分类号： H01L21/76254

摘要： A microstructure of the semiconductor on insulator type with different patterns is produced by forming a stacked uniform structure including a plate forming a substrate, a continuous insulative layer and a semiconductor layer. The continuous insulative layer is a stack of at least three elementary layers, including a bottom elementary layer, at least one intermediate elementary layer, and a top elementary layer overlying the semiconductor layer, where at least one of the bottom elementary layer and the top elementary layer being of an insulative material. In the stacked uniform structure, at least two patterns are differentiated by modifying at least one of the elementary layers in one of the patterns so that the elementary layer has a significantly different physical or chemical property between the two patterns, where at least one of the bottom and top elementary layer is an insulative material that remains unchanged.

摘要翻译： 通过形成包括形成衬底的板，连续绝缘层和半导体层的层叠均匀结构，来产生具有不同图案的绝缘体半导体型微结构。 连续绝缘层是至少三个基本层的堆叠，包括底部基本层，至少一个中间基本层和覆盖半导体层的顶部基本层，其中底部基本层和顶部基本层中的至少一个 层是绝缘材料。 在层叠的均匀结构中，通过修改其中一个图案中的至少一个基本层来区分至少两个图案，使得元件层在两个图案之间具有显着不同的物理或化学特性，其中至少一个 底部和顶部基本层是保持不变的绝缘材料。

公开(公告)号：US07951659B2

公开(公告)日：2011-05-31

申请号：US12505161

申请日：2009-07-17

申请人： Younes Lamrani ,  Jean-Charles Barbe ,  Marek Kostrzewa

发明人： Younes Lamrani ,  Jean-Charles Barbe ,  Marek Kostrzewa

IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L21/337 ,  H01L21/76 ,  H01L21/20 ,  H01L21/36

CPC分类号： H01L29/1054 ,  H01L21/823807 ,  H01L21/84

摘要： A method of forming a microelectronic device comprising, on a same support: at least one semi-conductor zone strained according to a first strain, and at least one semi-conductor zone strained according to a second strain, different to the first strain, comprising: the formation of semi-conductor zones above a pre-strained layer, then trenches extending through the thickness of the pre-strained layer, the dimensions and the layout of the semi-conductor zones as a function of the layout and the dimensions of the trenches being so as to obtain semi-conductor zones having a strain of the same type as that of the pre-strained layer and semi-conductor zones having a strain of a different type to that of the pre-strained layer.

摘要翻译： 一种形成微电子器件的方法，包括在相同的支撑件上：根据第一应变应变的至少一个半导体区域和根据与第一应变不同的第二应变应变的至少一个半导体区域，包括 ：在预应变层上形成半导体区，然后在预应变层的厚度上延伸沟槽，半导体区的尺寸和布局作为布局和尺寸的函数 沟槽以获得具有与预应变层相同类型的应变的半导体区域和具有与预应变层的不同类型的应变的半导体区域。

公开(公告)号：US20110233732A1

公开(公告)日：2011-09-29

申请号：US13059651

申请日：2009-08-31

申请人： Thomas Goislard De Monsabert ,  Chrystel Deguet ,  Jean Dijon ,  Marek Kostrzewa

发明人： Thomas Goislard De Monsabert ,  Chrystel Deguet ,  Jean Dijon ,  Marek Kostrzewa

IPC分类号： H01L29/06 ,  H01L29/02 ,  H01L21/762

CPC分类号： F02D13/02 ,  B81C1/00349 ,  B82Y10/00 ,  H01L21/187 ,  H01L21/76879 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/53276 ,  H01L25/0657 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L51/001 ,  H01L51/0045 ,  H01L2221/1094 ,  H01L2924/0002 ,  Y02T10/18 ,  H01L2924/00

摘要： A substrate configured to support at least one electronic or electromechanical component and one or more nano-elements, formed with a base support, with a catalytic system, with a barrier layer, and with a layer configured to receive the electronic or electromechanical component, in single-crystal Si or in Ge or in a mixture of these materials. The catalytic system lies on the base support without any contact with the layer configured to receive electronic or electromechanical component and the barrier layer is sandwiched between the catalytic system and the layer configured to receive the electronic or electromechanical component. This barrier layer is without any contact with the base support.

摘要翻译： 一种基板，被配置为支撑至少一个电子或机电部件以及一个或多个纳米元件，所述纳米元件形成有基底支撑件，催化系统与阻挡层，以及被配置为接纳电子或机电部件的层， 单晶Si或Ge或这些材料的混合物。 催化系统位于基座支撑件上，而与被配置成接收电子或机电部件的层没有任何接触，并且阻挡层夹在催化系统和构造成接收电子或机电部件的层之间。 该阻挡层没有与基底支撑件的任何接触。

公开(公告)号：US07947564B2

公开(公告)日：2011-05-24

申请号：US11857130

申请日：2007-09-18

申请人： Marek Kostrzewa ,  Hubert Moriceau ,  Marc Zussy

发明人： Marek Kostrzewa ,  Hubert Moriceau ,  Marc Zussy

IPC分类号： H01L21/76

CPC分类号： H01L21/76254 ,  B81C1/00357

摘要： A method of fabricating a mixed microtechnology structure includes providing a provisional substrate including a sacrificial layer on which is formed a mixed layer including at least first patterns of a first material and second patterns of a second material different from the first material, where the first and second patterns reside adjacent the sacrificial layer. The sacrificial layer is removed exposing a mixed surface of the mixed layer, the mixed surface including portions of the first patterns and portions of the second patterns. A continuous is formed covering layer of a third material on the mixed surface by direct bonding.

摘要翻译： 制造混合微技术结构的方法包括提供包括牺牲层的临时衬底，其上形成有至少包括第一材料的第一图案和不同于第一材料的第二材料的第二图案的混合层，其中第一和 第二图案位于牺牲层附近。 消除牺牲层暴露混合层的混合表面，混合表面包括第一图案的部分和第二图案的部分。 连续地通过直接粘合在混合表面上形成第三材料的覆盖层。

公开(公告)号：US07422958B2

公开(公告)日：2008-09-09

申请号：US11766463

申请日：2007-06-21

申请人： Marek Kostrzewa ,  Fabrice Letertre

发明人： Marek Kostrzewa ,  Fabrice Letertre

IPC分类号： H01L21/76

CPC分类号： H01L21/76254

摘要： A method for fabricating a mixed substrate that include insulating material layer portions buried in a substrate of semiconductor material. The method includes providing a support substrate made of semiconductor material and having a front face that includes open cavities; providing a layer of an insulating material upon the front face of the support substrate and into the cavities; polishing the layer to provide a perfectly planar surface; bonding a source substrate to the planar surface of the support substrate; withdrawing a portion of the source substrate to provide an assembly having a thin useful or active layer upon the insulating layer of the support substrate; and heat treating the assembly in a selected atmosphere at a temperature and for a time sufficient to diffuse atoms from the insulating layer and through the thin layer to reduce the thickness of the insulating layer while retaining the insulating material in the cavities of the support substrate.

摘要翻译： 一种制造混合衬底的方法，该混合衬底包括埋在半导体材料的衬底中的绝缘材料层部分。 该方法包括提供由半导体材料制成并具有包括开放空腔的前表面的支撑衬底; 在支撑基板的前表面上提供绝缘材料层并进入空腔; 抛光该层以提供完美平坦的表面; 将源极基板接合到所述支撑基板的平坦表面; 退出源基板的一部分以提供在支撑基板的绝缘层上具有薄的有用或有源层的组件; 并且在选定的气氛中，在足以从绝缘层扩散原子并通过薄层的温度和时间内对组件进行热处理，以在将绝缘材料保持在支撑衬底的空腔中的同时减小绝缘层的厚度。

公开(公告)号：US20100041205A1

公开(公告)日：2010-02-18

申请号：US12505161

申请日：2009-07-17

申请人： Younes LAMRANI ,  Jean-Charles Barbe ,  Marek Kostrzewa

发明人： Younes LAMRANI ,  Jean-Charles Barbe ,  Marek Kostrzewa

IPC分类号： H01L21/762

CPC分类号： H01L29/1054 ,  H01L21/823807 ,  H01L21/84

摘要： A method of forming a microelectronic device comprising, on a same support: at least one semi-conductor zone strained according to a first strain, and at least one semi-conductor zone strained according to a second strain, different to the first strain, comprising: the formation of semi-conductor zones above a pre-strained layer, then trenches extending through the thickness of the pre-strained layer, the dimensions and the layout of the semi-conductor zones as a function of the layout and the dimensions of the trenches being so as to obtain semi-conductor zones having a strain of the same type as that of the pre-strained layer and semi-conductor zones having a strain of a different type to that of the pre-strained layer.

摘要翻译： 一种形成微电子器件的方法，包括在相同的支撑件上：根据第一应变应变的至少一个半导体区域和根据与第一应变不同的第二应变应变的至少一个半导体区域，包括 ：在预应变层上形成半导体区，然后在预应变层的厚度上延伸沟槽，半导体区的尺寸和布局作为布局和尺寸的函数 沟槽以获得具有与预应变层相同类型的应变的半导体区域和具有与预应变层的不同类型的应变的半导体区域。

公开(公告)号：US20080079123A1

公开(公告)日：2008-04-03

申请号：US11857130

申请日：2007-09-18

申请人： Marek Kostrzewa ,  Hubert Moriceau ,  Marc Zussy

发明人： Marek Kostrzewa ,  Hubert Moriceau ,  Marc Zussy

IPC分类号： H01L23/58 ,  H01L21/31

CPC分类号： H01L21/76254 ,  B81C1/00357

摘要： A method of fabricating a mixed microtechnology structure includes providing a provisional substrate including a sacrificial layer on which is formed a mixed layer including at least first patterns of a first material and second patterns of a second material different from the first material, where the first and second patterns reside adjacent the sacrificial layer. The sacrificial layer is removed exposing a mixed surface of the mixed layer, the mixed surface including portions of the first patterns and portions of the second patterns. A continuous is formed covering layer of a third material on the mixed surface by direct bonding.

摘要翻译： 制造混合微技术结构的方法包括提供包括牺牲层的临时衬底，其上形成有至少包括第一材料的第一图案和不同于第一材料的第二材料的第二图案的混合层，其中第一和 第二图案位于牺牲层附近。 消除牺牲层暴露混合层的混合表面，混合表面包括第一图案的部分和第二图案的部分。 连续地通过直接粘合在混合表面上形成第三材料的覆盖层。