公开(公告)号：US4963501A

公开(公告)日：1990-10-16

申请号：US412253

申请日：1989-09-25

申请人： Frank J. Ryan ,  James W. Penney ,  Aditya K. Gupta

发明人： Frank J. Ryan ,  James W. Penney ,  Aditya K. Gupta

IPC分类号： H01L21/285 ,  H01L21/338 ,  H01L21/8252 ,  H01L29/423 ,  H01L29/78 ,  H01L29/812

CPC分类号： H01L29/66871 ,  H01L21/28587 ,  H01L21/8252 ,  H01L29/42316 ,  H01L29/78 ,  H01L29/812 ,  Y10S148/015 ,  Y10S148/111 ,  Y10S148/131 ,  Y10S148/14 ,  Y10S438/951

摘要： Methods for reducing linewidths of Field Effect Transistors (FETs) and making FETs with 0.5 to 0.15 .mu.m effective gate lengths are used separately or in a combined process sequence, that combines enhancement/depletion mode and microwave Metal-Semiconductors FETs (MESFETs) on the same GaAs chip. Photoresist linewidths are used to form dummy or substitutional gates using optical lithography with no deliberate overexposures. The dummy gate may be used as a mask for N+ implantation. The photoresist linewidth is then reduced in its lateral basewidth while preserving its height to basewidth aspect ratio in an isotropic oxygen plasma etch. A nonconformal dielectric film of silicon monoxide is deposited over the photoresist linewidth patterns. Dielectric reverse liftoff of the SiO pattern transfer dielectric provides a self-aligned stencil mask with respect to the N+/N- interfaces. The SiO stencil is also a dielectric spacer with respect to the N+/N- interfaces. The implantation profile's spatial variation with respect to the dielectric spacer dimension can be engineered to fabricate a lightly doped drain (LDD) MESFET. Finally, a Microwave Enhancement Depletion Integrated Circuit (MEDIC) process sequence mixes low threshold voltage digital MESFETs with higher threshold voltage microwave MESFETs.

摘要翻译： 使用场效应晶体管（FET）的线宽减小和制造具有0.5至0.15微米有效栅极长度的FET的方法可以单独使用或以组合工艺顺序进行使用，其结合了增强/耗尽模式和微波金属半导体FET（MESFET） 相同的GaAs芯片。 使用光刻胶线宽使用光刻法而没有故意的过度曝光形成虚拟或替代门。 虚拟栅极可以用作N +注入的掩模。 然后在其各向同性氧等离子体蚀刻中将光致抗蚀剂线宽降低到其横向基底宽度，同时保持其高度与基线纵横比。 在光致抗蚀剂线宽图案上沉积一氧化硅的非共形介电膜。 SiO型转印电介质的电介质反向剥离提供了相对于N + / N-界面的自对准模版掩模。 SiO模板也是相对于N + / N-界面的电介质间隔物。 相对于电介质间隔物尺寸的注入轮廓的空间变化可以被设计成制造轻掺杂漏极（LDD）MESFET。 最后，微波增强耗尽集成电路（MEDIC）处理顺序将低阈值电压数字MESFET与较高阈值电压微波MESFET混合。

公开(公告)号：US4731339A

公开(公告)日：1988-03-15

申请号：US899574

申请日：1986-08-25

申请人： Frank J. Ryan ,  Man-Chung F. Chang ,  Dennis A. Williams ,  Richard P. Vahrenkamp

发明人： Frank J. Ryan ,  Man-Chung F. Chang ,  Dennis A. Williams ,  Richard P. Vahrenkamp

IPC分类号： H01L21/338 ,  B44C1/22

CPC分类号： H01L29/66871

摘要： A single-level photoresist process is used to make metal-semiconductor field-effect transistors (MESFETs) having more uniform threshold voltages. An N.sup.- layer is formed in a semi-insulating semiconductor, followed by formation of a dummy gate using a single-level photoresist process. Using the dummy gate as a mask, ions are implanted to form an N.sup.+ region. The length of the dummy gate is then reduced by plasma etching. A dielectric is deposited over the N.sup.+ region, the N.sup.+ /N.sup.- interface, and the exposed portion of the N.sup.- layer. The dummy gate is lifted off to define a self-aligned, submicron gate opening. The gate opening on the N.sup.- layer is reactive ion etched to obtain the desired threshold voltage, and covered with a Schottky gate metal deposit.

摘要翻译： 使用单级光刻胶工艺来制造具有更均匀阈值电压的金属半导体场效应晶体管（MESFET）。 在半绝缘半导体中形成N-层，然后使用单层光致抗蚀剂工艺形成虚拟栅极。 使用伪栅极作为掩模，注入离子以形成N +区域。 然后通过等离子体蚀刻减少虚拟栅极的长度。 电介质沉积在N +区域上，N + / N-界面和N层的暴露部分。 虚拟门被提起以限定自对准的亚微米门开口。 N-层上的栅极开口被反应离子蚀刻以获得所需的阈值电压，并用肖特基栅极金属沉积物覆盖。