公开(公告)号：US5342476A

公开(公告)日：1994-08-30

申请号：US7348

申请日：1993-01-21

申请人： John L. Cain

发明人： John L. Cain

IPC分类号： H01L21/3213 ,  B44C1/22

CPC分类号： H01L21/32137 ,  Y10S148/131

摘要： Disclosed are methods for reducing the degree of underetching and particulate contamination occurring during dry non-isotropic etching of a polycide layer on the surface of a silicon wafer maintained in a wafer holder wherein the backside of the holder is cooled with a stream of helium gas. Specifically, in the disclosed methods, dry non-isotropic etching of the polycide layer is conducted either in the absence of backside cooling or the helium gas flow utilized in backside cooling is maintained at a pressure of no more than 3 torr.

摘要翻译： 公开了用于降低在保持在晶片保持器中的硅晶片的表面上的多晶硅层的干非均质蚀刻期间发生的去抛光和微粒污染的程度的方法，其中保持器的背面用氦气流冷却。 具体地说，在所公开的方法中，在不存在背面冷却的情况下进行多晶硅层的干非均相蚀刻，或者在背面冷却中使用的氦气流保持不超过3托的压力。

公开(公告)号：US5171718A

公开(公告)日：1992-12-15

申请号：US639325

申请日：1991-01-09

申请人： Akira Ishibashi ,  Yoshifumi Mori ,  Kenji Funato

发明人： Akira Ishibashi ,  Yoshifumi Mori ,  Kenji Funato

IPC分类号： G03F7/004 ,  G03F7/20

CPC分类号： G03F7/004 ,  G03F7/2041 ,  Y10S148/10 ,  Y10S148/131 ,  Y10S148/137 ,  Y10S438/949

摘要： A fine pattern formation using an electron beam induced resist, and use of the resist in making semiconductor devices are disclosed. Collimated electron beam is irradiated and scanned along a desired pattern on a layer on which a resist layer of a desired pattern is deposited under an atmosphere containing a starting material layer for the resist. The resist thus deposited is partially removed by reactive ion etching to remove the skirt like portion of the resist layer, or totally removed by reactive ion etching during or after processing by using the resist layer as a processing mask. Since the resist layer width is determined by a diameter of the collimated electron beam, line width of less than hundred .ANG. can be directly drawn. There are also disclosed processes using the resist layer in manufacturing semiconductor devices.

摘要翻译： 公开了使用电子束感应抗蚀剂的精细图案形成，以及在制造半导体器件中使用抗蚀剂。 沿着期望的图案沿着期望的图案照射准直的电子束，在其上沉积有所需图案的抗蚀剂层的层上，在含有抗蚀剂的起始材料层的气氛下。 通过反应离子蚀刻部分去除由此沉积的抗蚀剂以去除抗蚀剂层的裙状部分，或者通过使用抗蚀剂层作为处理掩模在处理期间或之后通过反应离子蚀刻完全除去。 由于抗蚀剂层宽度由准直电子束的直径确定，所以可以直接绘制小于100的棱线宽度。 还公开了在制造半导体器件中使用抗蚀剂层的工艺。

公开(公告)号：US5084419A

公开(公告)日：1992-01-28

申请号：US327602

申请日：1989-03-23

申请人： Masato Sakao

发明人： Masato Sakao

IPC分类号： H01L21/304 ,  H01L21/20 ,  H01L21/302 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/76 ,  H01L21/762

CPC分类号： H01L21/02024 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/31055 ,  H01L21/76294 ,  Y10S148/051 ,  Y10S148/131

摘要： A method of manufacturing a semiconductor device in which a portion of a monocrystalline silicon layer protruded from a surface of an insulating member is polished up to the surface by a chemical-mechanical polishing is disclosed. A polycrystalline silicon layer and a leveling material are formed in sequence on the protruded portion of the monocrystalline silicon layer and on an exposed part of the surface of the insulating member, and a reactive ion etching and the chemical-mechanical polishing are carried out.

摘要翻译： 公开了一种制造半导体器件的方法，其中通过化学机械抛光将从绝缘构件的表面突出的单晶硅层的一部分抛光到表面。 在单晶硅层的突出部分和绝缘构件的表面的暴露部分上依次形成多晶硅层和调平材料，并进行反应离子蚀刻和化学机械抛光。

公开(公告)号：US4963501A

公开(公告)日：1990-10-16

申请号：US412253

申请日：1989-09-25

申请人： Frank J. Ryan ,  James W. Penney ,  Aditya K. Gupta

发明人： Frank J. Ryan ,  James W. Penney ,  Aditya K. Gupta

IPC分类号： H01L21/285 ,  H01L21/338 ,  H01L21/8252 ,  H01L29/423 ,  H01L29/78 ,  H01L29/812

CPC分类号： H01L29/66871 ,  H01L21/28587 ,  H01L21/8252 ,  H01L29/42316 ,  H01L29/78 ,  H01L29/812 ,  Y10S148/015 ,  Y10S148/111 ,  Y10S148/131 ,  Y10S148/14 ,  Y10S438/951

摘要： Methods for reducing linewidths of Field Effect Transistors (FETs) and making FETs with 0.5 to 0.15 .mu.m effective gate lengths are used separately or in a combined process sequence, that combines enhancement/depletion mode and microwave Metal-Semiconductors FETs (MESFETs) on the same GaAs chip. Photoresist linewidths are used to form dummy or substitutional gates using optical lithography with no deliberate overexposures. The dummy gate may be used as a mask for N+ implantation. The photoresist linewidth is then reduced in its lateral basewidth while preserving its height to basewidth aspect ratio in an isotropic oxygen plasma etch. A nonconformal dielectric film of silicon monoxide is deposited over the photoresist linewidth patterns. Dielectric reverse liftoff of the SiO pattern transfer dielectric provides a self-aligned stencil mask with respect to the N+/N- interfaces. The SiO stencil is also a dielectric spacer with respect to the N+/N- interfaces. The implantation profile's spatial variation with respect to the dielectric spacer dimension can be engineered to fabricate a lightly doped drain (LDD) MESFET. Finally, a Microwave Enhancement Depletion Integrated Circuit (MEDIC) process sequence mixes low threshold voltage digital MESFETs with higher threshold voltage microwave MESFETs.

摘要翻译： 使用场效应晶体管（FET）的线宽减小和制造具有0.5至0.15微米有效栅极长度的FET的方法可以单独使用或以组合工艺顺序进行使用，其结合了增强/耗尽模式和微波金属半导体FET（MESFET） 相同的GaAs芯片。 使用光刻胶线宽使用光刻法而没有故意的过度曝光形成虚拟或替代门。 虚拟栅极可以用作N +注入的掩模。 然后在其各向同性氧等离子体蚀刻中将光致抗蚀剂线宽降低到其横向基底宽度，同时保持其高度与基线纵横比。 在光致抗蚀剂线宽图案上沉积一氧化硅的非共形介电膜。 SiO型转印电介质的电介质反向剥离提供了相对于N + / N-界面的自对准模版掩模。 SiO模板也是相对于N + / N-界面的电介质间隔物。 相对于电介质间隔物尺寸的注入轮廓的空间变化可以被设计成制造轻掺杂漏极（LDD）MESFET。 最后，微波增强耗尽集成电路（MEDIC）处理顺序将低阈值电压数字MESFET与较高阈值电压微波MESFET混合。

公开(公告)号：US4849376A

公开(公告)日：1989-07-18

申请号：US137482

申请日：1987-12-23

申请人： Matthew L. Balzan ,  Arthur E. Geissberger ,  Robert A. Sadler

发明人： Matthew L. Balzan ,  Arthur E. Geissberger ,  Robert A. Sadler

IPC分类号： C23F4/00 ,  H01L21/285 ,  H01L21/3213 ,  H01L21/338 ,  H01L21/8252 ,  H01L29/47

CPC分类号： H01L29/66878 ,  H01L21/28581 ,  H01L21/28587 ,  H01L21/32136 ,  H01L21/8252 ,  H01L29/475 ,  Y10S148/051 ,  Y10S148/105 ,  Y10S148/131 ,  Y10S438/945

摘要： A process for manufacturing GaAs FET's having refractory metal gates provides for reducing the size of the gate relative to a mask by an etch sequence which results in precisely controlled and repeatable self-limited undercutting of the mask. A reactive ion etch of the refractory metal in a CF.sub.4 O.sub.2 plasma containing an inert gas provides the self-limiting undercut at a pressure in the range of 175-250 mTorr when the power is less than 0.15 W/cm.sup.2. Preceeding the undercut, an anisotropic RIE in a CF.sub.4 plasma can be employed to clear unmasked areas of the refractory metal and an initial sputter cleaning in argon improves the quality of the initial etch.

摘要翻译： 用于制造具有难熔金属栅极的GaAs FET的工艺提供了通过蚀刻序列来减小栅极相对于掩模的尺寸，这导致了掩模的精确控制和可重复的自限制底切。 含有惰性气体的CF4O2等离子体中的难熔金属的反应离子蚀刻在功率小于0.15W / cm 2时在175-250mTorr的压力下提供自限制底切。 在底切之前，可以使用CF4等离子体中的各向异性RIE来清除难熔金属的未掩蔽区域，并且在氩气中的初始溅射清洗改善了初始蚀刻的质量。

公开(公告)号：US4849368A

公开(公告)日：1989-07-18

申请号：US146664

申请日：1988-01-21

申请人： Yoshimi Yamashita ,  Kinjiro Kosemura ,  Hidetoshi Ishiwari ,  Sumio Yamamoto ,  Shigeru Kuroda

发明人： Yoshimi Yamashita ,  Kinjiro Kosemura ,  Hidetoshi Ishiwari ,  Sumio Yamamoto ,  Shigeru Kuroda

IPC分类号： H01L21/306 ,  H01L21/8236 ,  H01L21/8252 ,  H01L27/06 ,  H01L29/778

CPC分类号： H01L27/0883 ,  H01L21/30621 ,  H01L21/8236 ,  H01L21/8252 ,  H01L27/0605 ,  H01L29/7787 ,  Y10S148/131 ,  Y10S148/168

摘要： Disclosed is a method of producing a compound semiconductor device comprising an enhancement-mode transistor and a depletion-mode transistor, each of which has a heterojunction and utilizes a two-dimensional electron gas. The method of producing the device comprises the steps of: forming an undoped GaAs channel layer on a semi-insulating GaAs substrate; forming an N-type AlGaAs electron-supply layer so as to form the heterojunction; forming an N-type GaAs layer; forming an AlGaAs layer; selectively etching the AlGaAs layer to form a recess; performing an etching treatment using an etchant which can etch rapidly GaAs and etch slowly AlGaAs to form simultaneously grooves for gate electrodes of the enhancement-mode transistor and the depletion-mode transistor, the bottoms of the grooves being in the N-type AlGaAs layer and the distance between the bottoms being equal to the thickness of the AlGaAs layer; and forming simultaneously the gate electrodes in the grooves.

公开(公告)号：US4818714A

公开(公告)日：1989-04-04

申请号：US127995

申请日：1987-12-02

申请人： Jacob D. Haskell

发明人： Jacob D. Haskell

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/265 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L29/6659 ,  H01L21/823814 ,  H01L29/6656 ,  H01L29/78 ,  Y10S148/106 ,  Y10S148/131 ,  Y10S257/90

摘要： An MOS structure and a method for making same, including the formation of el-shaped shielding members used to form one or more lightly doped drain regions to avoid short channel and punch-through problems is disclosed which comprises forming a shielding layer of an insulating material over a gate electrode on a substrate; forming another layer of a dissimilar material over the shielding layer; anisotropically etching the layer of dissimilar material to form spacer portions adjacent the sidewalls of the gate electrode; removing the portions of the shielding layer not masked by the spacer portions, leaving one or more el-shaped shielding members; removing the spacer portions; N+ or P+ implanting the substrate at a sufficiently low energy to prevent penetration of the dopant through the el-shaped shielding member to form a highly doped source/drain region in the substrate not shielded by the el-shaped shielding member or the gate electrode; N- or P- implanting the substrate at a sufficiently high energy to penetrate through the el-shaped shielding member to form a lightly doped source/drain region in the portion of the substrate adjacent the P+ or N+ source/drain regions and separating the channel region of the substrate beneath the gate electrode from the P+ or N+ source/drain region.

摘要翻译： 公开了一种MOS结构及其制造方法，包括形成用于形成一个或多个轻掺杂漏极区的el形屏蔽构件以避免短沟道和穿通问题，其包括形成绝缘材料的屏蔽层 在基板上的栅电极上; 在所述屏蔽层上形成不同材料的另一层; 各向异性地蚀刻不同材料层以形成邻近栅电极的侧壁的间隔部分; 去除未被隔离物部分掩蔽的屏蔽层的部分，留下一个或多个el形屏蔽构件; 移除间隔部分; N +或P +以足够低的能量注入衬底以防止掺杂剂穿过el形屏蔽构件，以在衬底中形成高度掺杂的源极/漏极区域，而不被EL形屏蔽构件或栅电极屏蔽; N或P-以足够高的能量注入衬底以穿透el形屏蔽构件，以在衬底的与P +或N +源极/漏极区相邻的部分中形成轻掺杂的源极/漏极区，并分离沟道 从P +或N +源极/漏极区域到栅电极下方的衬底的区域。

公开(公告)号：US4646424A

公开(公告)日：1987-03-03

申请号：US761937

申请日：1985-08-02

申请人： Harold G. Parks ,  George E. Possin

发明人： Harold G. Parks ,  George E. Possin

IPC分类号： C23C14/08 ,  C23C14/06 ,  C23C14/14 ,  G02F1/133 ,  G02F1/136 ,  G02F1/1368 ,  H01L21/336 ,  H01L27/12 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/66765 ,  G02F1/1368 ,  H01L29/4908 ,  Y10S148/131

摘要： The gate electrode in an inverted field effect transistor (FET) is fabricated with titanium to provide an FET which is particularly suitable for use as the switching element in a matrix addressed liquid crystal display. More particularly, the resist employed in gate electrode patterning is plasma ashed in an oxygen atmosphere to toughen the titanium gate material and render it more amenable to subsequent processing steps.

摘要翻译： 反向场效应晶体管（FET）中的栅电极由钛制成，以提供特别适合用作矩阵寻址液晶显示器中的开关元件的FET。 更具体地，用于栅极电极图案化的抗蚀剂是在氧气氛中等离子体灰化以增韧钛栅极材料并使其更适于随后的处理步骤。

公开(公告)号：US4338138A

公开(公告)日：1982-07-06

申请号：US126611

申请日：1980-03-03

申请人： Joseph R. Cavaliere ,  Cheng T. Horng ,  Richard R. Konian ,  Hans S. Rupprecht ,  Robert O. Schwenker

发明人： Joseph R. Cavaliere ,  Cheng T. Horng ,  Richard R. Konian ,  Hans S. Rupprecht ,  Robert O. Schwenker

IPC分类号： H01L21/8222 ,  H01L21/033 ,  H01L21/285 ,  H01L21/331 ,  H01L21/762 ,  H01L27/06 ,  H01L29/73 ,  H01L29/732 ,  H01L21/263 ,  H01L21/203 ,  H01L21/22 ,  H01L21/31

CPC分类号： H01L29/66272 ,  H01L21/033 ,  H01L21/28525 ,  H01L21/76229 ,  H01L21/76232 ,  H01L29/7325 ,  Y10S148/131

摘要： An improved bipolar transistor structure formed in a very small area of a thin epitaxial layer on a planar surface of a silicon substrate of first conductivity type, said very small area of the thin epitaxial layer having vertical sidewalls extending to the planar surface of said substrate, said area of thin epitaxial layers containing in the order recited a shallow depth emitter region of a second conductivity type having an exposed planar surface, a shallow depth base region of said first conductivity type, and a shallow depth active collector region of said second conductivity type, an elongated region of said first conductivity type surrounding said emitter, base and active collector regions, said elongated region being contained within and coextensive with said vertical sidewalls of said small area of said thin epitaxial layer, whereby the base collector capacitance is materially reduced due to the very small area of the base-collector junction. Also disclosed is a process and alternative process, for fabricating an improved bipolar transistor structure.

摘要翻译： 一种改进的双极晶体管结构，其形成在第一导电类型的硅衬底的平坦表面上的薄外延层的非常小的区域中，所述薄外延层的非常小的面积具有延伸到所述衬底的平坦表面的垂直侧壁， 所述薄外延层的区域包含按顺序列出的具有暴露平面的第二导电类型的浅深度发射极区域，所述第一导电类型的浅深度基底区域和所述第二导电类型的浅深度有源集电极区域 围绕所述发射极，基极和主动集电极区域的所述第一导电类型的细长区域，所述细长区域包含在所述薄外延层的所述小区域的所述垂直侧壁内并与之共同延伸，由此基极集电极电容由于 到基极 - 集电极结的非常小的区域。 还公开了用于制造改进的双极晶体管结构的工艺和替代工艺。

公开(公告)号：US4256514A

公开(公告)日：1981-03-17

申请号：US957604

申请日：1978-11-03

申请人： Hans B. Pogge

发明人： Hans B. Pogge

IPC分类号： H01L29/73 ,  H01L21/033 ,  H01L21/22 ,  H01L21/265 ,  H01L21/266 ,  H01L21/28 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/331 ,  H01L21/76 ,  H01L21/762 ,  H01L21/763 ,  H01L21/768 ,  H01L21/822 ,  H01L27/04 ,  H01L21/26 ,  H01L21/285 ,  H01L21/308

CPC分类号： H01L21/743 ,  H01L21/0337 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/76232 ,  H01L21/763 ,  Y10S148/131 ,  Y10T428/23929 ,  Y10T428/23979

摘要： A method for forming a narrow dimensioned, for example, submicron, region on a silicon body that involves forming on the silicon body regions having substantially horizontal surfaces and substantially vertical surfaces. A layer of a very narrow dimension is formed both on the substantially horizontal and substantially vertical surfaces. Reactive ion etching is applied to the layer to substantially remove the horizontal layer while leaving the vertical layer substantially intact. The vertical layer dimension is adjusted depending upon the original thickness of the layer applied.

摘要翻译： 一种在硅体上形成窄尺寸例如亚微米区域的方法，其涉及在具有基本上水平的表面和基本上垂直的表面的硅体区域上形成。 在基本水平和基本上垂直的表面上形成非常窄的尺寸的层。 对层进行反应离子蚀刻，以基本上除去水平层，同时使垂直层基本上保持不变。 垂直层尺寸根据施加的层的原始厚度进行调整。