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公开(公告)号：US20110296428A1
公开(公告)日：2011-12-01
申请号：US12789062
申请日：2010-05-27
IPC分类号： G06F9/50
CPC分类号： G06F9/3851 , G06F9/30098 , G06F9/30123 , G06F9/30138 , G06F9/384 , G06F9/5016
摘要： A method, system, and computer usable program product for improved register allocation in a simultaneous multithreaded processor. A determination is made that a thread of an application in the data processing environment needs more physical registers than are available to allocate to the thread. The thread is configured to utilize a logical register that is mapped to a memory register. The thread is executed utilizing the physical registers and the memory registers.
摘要翻译： 一种用于改进同时多线程处理器中的寄存器分配的方法，系统和计算机可用程序产品。 确定数据处理环境中的应用程序的线程需要比可用于分配给线程的物理寄存器更多的物理寄存器。 该线程被配置为利用映射到存储器寄存器的逻辑寄存器。 使用物理寄存器和存储器寄存器执行线程。
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公开(公告)号：US09501285B2
公开(公告)日：2016-11-22
申请号：US12789062
申请日：2010-05-27
CPC分类号： G06F9/3851 , G06F9/30098 , G06F9/30123 , G06F9/30138 , G06F9/384 , G06F9/5016
摘要： A method, system, and computer usable program product for improved register allocation in a simultaneous multithreaded processor. A determination is made that a thread of an application in the data processing environment needs more physical registers than are available to allocate to the thread. The thread is configured to utilize a logical register that is mapped to a memory register. The thread is executed utilizing the physical registers and the memory registers.
摘要翻译： 一种用于改进同时多线程处理器中的寄存器分配的方法，系统和计算机可用程序产品。 确定数据处理环境中的应用程序的线程需要比可用于分配给线程的物理寄存器更多的物理寄存器。 该线程被配置为利用映射到存储器寄存器的逻辑寄存器。 使用物理寄存器和存储器寄存器执行线程。
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公开(公告)号：US09934079B2
公开(公告)日：2018-04-03
申请号：US12789082
申请日：2010-05-27
申请人： John Bruce Carter , Elmootazbellah Nabil Elnozahy , Ahmed Gheith , Eric Van Hansbergen , Karthick Rajamani , William Evan Speight , Lixin Zhang
发明人： John Bruce Carter , Elmootazbellah Nabil Elnozahy , Ahmed Gheith , Eric Van Hansbergen , Karthick Rajamani , William Evan Speight , Lixin Zhang
CPC分类号： G06F9/544
摘要： A system, and computer usable program product for fast remote communication and computation between processors are provided in the illustrative embodiments. A direct core to core communication unit (DCC) is configured to operate with a first processor, the first processor being a remote processor. A memory associated with the DCC receives a set of bytes, the set of bytes being sent from a second processor. An operation specified in the set of bytes is executed at the remote processor such that the operation is invoked without causing a software thread to execute.
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公开(公告)号：US20120191946A1
公开(公告)日：2012-07-26
申请号：US13413787
申请日：2012-03-07
申请人： John Bruce Carter , Elmootazbellah Nabil Elnozahy , Ahmed Gheith , Eric Van Hensbergen , Karthick Rajamani , William Evan Speight , Lixin Zhang
发明人： John Bruce Carter , Elmootazbellah Nabil Elnozahy , Ahmed Gheith , Eric Van Hensbergen , Karthick Rajamani , William Evan Speight , Lixin Zhang
CPC分类号： G06F9/544
摘要： A method for fast remote communication and computation between processors is provided in the illustrative embodiments. A direct core to core communication unit (DCC) is configured to operate with a first processor, the first processor being a remote processor. A memory associated with the DCC receives a set of bytes, the set of bytes being sent from a second processor. An operation specified in the set of bytes is executed at the remote processor such that the operation is invoked without causing a software thread to execute.
摘要翻译： 在说明性实施例中提供了用于处理器之间的快速远程通信和计算的方法。 核心通信单元（DCC）的直接核心被配置为与第一处理器一起操作，第一处理器是远程处理器。 与DCC相关联的存储器接收一组字节，该字节集合是从第二处理器发送的。 在远程处理器中执行在该组字节中指定的操作，使得调用操作而不使软件线程执行。
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公开(公告)号：US07698508B2
公开(公告)日：2010-04-13
申请号：US11674960
申请日：2007-02-14
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F12/0804 , G06F12/0817
摘要： A system and method for cache management in a data processing system. The data processing system includes a processor and a memory hierarchy. The memory hierarchy includes at least an upper memory cache, at least a lower memory cache, and a write-back data structure. In response to replacing data from the upper memory cache, the upper memory cache examines the write-back data structure to determine whether or not the data is present in the lower memory cache. If the data is present in the lower memory cache, the data is replaced in the upper memory cache without casting out the data to the lower memory cache.
摘要翻译： 一种用于数据处理系统中缓存管理的系统和方法。 数据处理系统包括处理器和存储器层级。 存储器层级至少包括上部存储器高速缓存，至少下部存储器高速缓存和回写数据结构。 响应于从上部存储器高速缓存替换数据，上部存储器高速缓存检查回写数据结构以确定数据是否存在于下部存储器高速缓存中。 如果数据存在于较低存储器高速缓存中，则数据将在上部存储器高速缓存中替换，而不会将数据丢弃到较低的内存高速缓存。
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6.发明授权Fast remote communication and computation between processors using store and load operations on direct core-to-core memory 有权在直接核心到内核存储器之间使用存储和加载操作的处理器之间的快速远程通信和计算公开(公告)号：US08799625B2
公开(公告)日：2014-08-05
申请号：US13413787
申请日：2012-03-07
申请人： John Bruce Carter , Elmootazbellah Nabil Elnozahy , Ahmed Gheith , Eric Van Hansbergen , Karthick Rajamani , William Evan Speight , Lixin Zhang
发明人： John Bruce Carter , Elmootazbellah Nabil Elnozahy , Ahmed Gheith , Eric Van Hansbergen , Karthick Rajamani , William Evan Speight , Lixin Zhang
IPC分类号： G06F9/30
CPC分类号： G06F9/544
摘要： A method for fast remote communication and computation between processors is provided in the illustrative embodiments. A direct core to core communication unit (DCC) is configured to operate with a first processor, the first processor being a remote processor. A memory associated with the DCC receives a set of bytes, the set of bytes being sent from a second processor. An operation specified in the set of bytes is executed at the remote processor such that the operation is invoked without causing a software thread to execute.
摘要翻译： 在说明性实施例中提供了用于处理器之间的快速远程通信和计算的方法。 核心通信单元（DCC）的直接核心被配置为与第一处理器一起操作，第一处理器是远程处理器。 与DCC相关联的存储器接收一组字节，该字节集合是从第二处理器发送的。 在远程处理器中执行在该组字节中指定的操作，使得调用操作而不使软件线程执行。
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公开(公告)号：US07546417B1
公开(公告)日：2009-06-09
申请号：US12173613
申请日：2008-07-15
CPC分类号： G06F12/0864 , G06F2212/1044
摘要： A method of accessing data from a cache is disclosed. Tag bits of data among sets and ways of cache lines are divided into common subtags and remaining subtags. Similarly, an access address tag is divided into an address common subtag and address remaining tag. When the index of an access address selects a set, a match comparison of the address common subtag and the selected set common subtag is performed. Also, the address remaining tag and selected set remaining subtags are compared for matching before the selected set and associated data is supplied to the requester.
摘要翻译： 公开了一种从缓存访问数据的方法。 标记数据组中的数据位和高速缓存行的方式分为常见的子标签和剩余子标签。 类似地，访问地址标签被分成地址共享子标签和地址剩余标签。 当访问地址的索引选择一个集合时，执行地址公共子标记和所选择的公共子标记的匹配比较。 此外，在选择的集合和相关联的数据被提供给请求者之前，比较地址剩余标签和选择的集合剩余子标签以进行匹配。
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公开(公告)号：US20130145210A1
公开(公告)日：2013-06-06
申请号：US13309402
申请日：2011-12-01
申请人： Jian Li , William Evan Speight
发明人： Jian Li , William Evan Speight
CPC分类号： G06F1/1692
摘要： For a flexible replication with skewed mapping in a multi-core chip, a request for a cache line is received, at a receiver core in the multi-core chip from a requester core in the multi-core chip. The receiver and requester cores comprise electronic circuits. The multi-core chip comprises a set of cores including the receiver and the requester cores. A target core is identified from the request to which the request is targeted. A determination is made whether the target core includes the requester core in a neighborhood of the target core, the neighborhood including a first subset of cores mapped to the target core according to a skewed mapping. The cache line is replicated, responsive to the determining being negative, from the target core to a replication core. The cache line is provided from the replication core to the requester core.
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公开(公告)号：US09026743B2
公开(公告)日：2015-05-05
申请号：US13460294
申请日：2012-04-30
申请人： Jian Li , William Evan Speight
发明人： Jian Li , William Evan Speight
CPC分类号： G06F1/1692
摘要： For a flexible replication with skewed mapping in a multi-core chip, a request for a cache line is received, at a receiver core in the multi-core chip from a requester core in the multi-core chip. The receiver and requester cores comprise electronic circuits. The multi-core chip comprises a set of cores including the receiver and the requester cores. A target core is identified from the request to which the request is targeted. A determination is made whether the target core includes the requester core in a neighborhood of the target core, the neighborhood including a first subset of cores mapped to the target core according to a skewed mapping. The cache line is replicated, responsive to the determining being negative, from the target core to a replication core. The cache line is provided from the replication core to the requester core.
摘要翻译： 对于在多核芯片中具有偏斜映射的灵活复制，在多核芯片中的请求者核心的多核芯片的接收器核心处接收对高速缓存行的请求。 接收机和请求者核心包括电子电路。 多核芯片包括一组核心，包括接收机和请求者核心。 从请求所针对的请求中识别目标核心。 确定目标核心是否在目标核心的邻域中包括请求者核心，该邻域包括根据偏斜映射映射到目标核心的核心的第一子集。 缓存行被复制，响应于确定为否定，从目标核心到复制核心。 高速缓存行从复制核心提供给请求者核心。
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公开(公告)号：US08966187B2
公开(公告)日：2015-02-24
申请号：US13309402
申请日：2011-12-01
申请人： Jian Li , William Evan Speight
发明人： Jian Li , William Evan Speight
CPC分类号： G06F1/1692
摘要： For a flexible replication with skewed mapping in a multi-core chip, a request for a cache line is received, at a receiver core in the multi-core chip from a requester core in the multi-core chip. The receiver and requester cores comprise electronic circuits. The multi-core chip comprises a set of cores including the receiver and the requester cores. A target core is identified from the request to which the request is targeted. A determination is made whether the target core includes the requester core in a neighborhood of the target core, the neighborhood including a first subset of cores mapped to the target core according to a skewed mapping. The cache line is replicated, responsive to the determining being negative, from the target core to a replication core. The cache line is provided from the replication core to the requester core.
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