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    REGISTER ALLOCATION TO THREADS
    4.
    发明申请
    REGISTER ALLOCATION TO THREADS 有权
    注册分配到线程

    公开(公告)号：US20110296428A1

    公开(公告)日：2011-12-01

    申请号：US12789062

    申请日：2010-05-27

    申请人： FREEMAN LEIGH RAWSON, III ,  William Evan Speight ,  Lixin Zhang

    发明人： FREEMAN LEIGH RAWSON, III ,  William Evan Speight ,  Lixin Zhang

    IPC分类号： G06F9/50

    CPC分类号： G06F9/3851 ,  G06F9/30098 ,  G06F9/30123 ,  G06F9/30138 ,  G06F9/384 ,  G06F9/5016

    摘要： A method, system, and computer usable program product for improved register allocation in a simultaneous multithreaded processor. A determination is made that a thread of an application in the data processing environment needs more physical registers than are available to allocate to the thread. The thread is configured to utilize a logical register that is mapped to a memory register. The thread is executed utilizing the physical registers and the memory registers.

    摘要翻译： 一种用于改进同时多线程处理器中的寄存器分配的方法，系统和计算机可用程序产品。 确定数据处理环境中的应用程序的线程需要比可用于分配给线程的物理寄存器更多的物理寄存器。 该线程被配置为利用映射到存储器寄存器的逻辑寄存器。 使用物理寄存器和存储器寄存器执行线程。

    System and method for reducing unnecessary cache operations
    5.
    发明授权
    System and method for reducing unnecessary cache operations 失效
    减少不必要的缓存操作的系统和方法

    公开(公告)号：US07698508B2

    公开(公告)日：2010-04-13

    申请号：US11674960

    申请日：2007-02-14

    申请人： Ramakrishnan Rajamony ,  Hazim Shafi ,  William Evan Speight ,  Lixin Zhang

    发明人： Ramakrishnan Rajamony ,  Hazim Shafi ,  William Evan Speight ,  Lixin Zhang

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0897 ,  G06F12/0804 ,  G06F12/0817

    摘要： A system and method for cache management in a data processing system. The data processing system includes a processor and a memory hierarchy. The memory hierarchy includes at least an upper memory cache, at least a lower memory cache, and a write-back data structure. In response to replacing data from the upper memory cache, the upper memory cache examines the write-back data structure to determine whether or not the data is present in the lower memory cache. If the data is present in the lower memory cache, the data is replaced in the upper memory cache without casting out the data to the lower memory cache.

    摘要翻译： 一种用于数据处理系统中缓存管理的系统和方法。 数据处理系统包括处理器和存储器层级。 存储器层级至少包括上部存储器高速缓存，至少下部存储器高速缓存和回写数据结构。 响应于从上部存储器高速缓存替换数据，上部存储器高速缓存检查回写数据结构以确定数据是否存在于下部存储器高速缓存中。 如果数据存在于较低存储器高速缓存中，则数据将在上部存储器高速缓存中替换，而不会将数据丢弃到较低的内存高速缓存。

    Register allocation to threads
    6.
    发明授权
    Register allocation to threads 有权
    注册线程分配

    公开(公告)号：US09501285B2

    公开(公告)日：2016-11-22

    申请号：US12789062

    申请日：2010-05-27

    申请人： Freeman Leigh Rawson, III ,  William Evan Speight ,  Lixin Zhang

    发明人： Freeman Leigh Rawson, III ,  William Evan Speight ,  Lixin Zhang

    IPC分类号： G06F9/50 ,  G06F9/38 ,  G06F9/30

    CPC分类号： G06F9/3851 ,  G06F9/30098 ,  G06F9/30123 ,  G06F9/30138 ,  G06F9/384 ,  G06F9/5016

    摘要： A method, system, and computer usable program product for improved register allocation in a simultaneous multithreaded processor. A determination is made that a thread of an application in the data processing environment needs more physical registers than are available to allocate to the thread. The thread is configured to utilize a logical register that is mapped to a memory register. The thread is executed utilizing the physical registers and the memory registers.

    摘要翻译： 一种用于改进同时多线程处理器中的寄存器分配的方法，系统和计算机可用程序产品。 确定数据处理环境中的应用程序的线程需要比可用于分配给线程的物理寄存器更多的物理寄存器。 该线程被配置为利用映射到存储器寄存器的逻辑寄存器。 使用物理寄存器和存储器寄存器执行线程。

    Method and system for reducing cache tag bits
    7.
    发明授权
    Method and system for reducing cache tag bits 失效
    减少缓存标签位的方法和系统

    公开(公告)号：US07546417B1

    公开(公告)日：2009-06-09

    申请号：US12173613

    申请日：2008-07-15

    申请人： Ramakrishnan Rajamony ,  William Evan Speight ,  Lixin Zhang

    发明人： Ramakrishnan Rajamony ,  William Evan Speight ,  Lixin Zhang

    IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

    CPC分类号： G06F12/0864 ,  G06F2212/1044

    摘要： A method of accessing data from a cache is disclosed. Tag bits of data among sets and ways of cache lines are divided into common subtags and remaining subtags. Similarly, an access address tag is divided into an address common subtag and address remaining tag. When the index of an access address selects a set, a match comparison of the address common subtag and the selected set common subtag is performed. Also, the address remaining tag and selected set remaining subtags are compared for matching before the selected set and associated data is supplied to the requester.

    摘要翻译： 公开了一种从缓存访问数据的方法。 标记数据组中的数据位和高速缓存行的方式分为常见的子标签和剩余子标签。 类似地，访问地址标签被分成地址共享子标签和地址剩余标签。 当访问地址的索引选择一个集合时，执行地址公共子标记和所选择的公共子标记的匹配比较。 此外，在选择的集合和相关联的数据被提供给请求者之前，比较地址剩余标签和选择的集合剩余子标签以进行匹配。

    Instruction set architecture extensions for performing power versus performance tradeoffs
    8.
    发明授权
    Instruction set architecture extensions for performing power versus performance tradeoffs 失效
    用于执行功率与性能折衷的指令集架构扩展

    公开(公告)号：US08589665B2

    公开(公告)日：2013-11-19

    申请号：US12788940

    申请日：2010-05-27

    申请人： John B. Carter ,  Jian Li ,  Karthick Rajamani ,  William E. Speight ,  Lixin Zhang

    发明人： John B. Carter ,  Jian Li ,  Karthick Rajamani ,  William E. Speight ,  Lixin Zhang

    IPC分类号： G06F9/00

    CPC分类号： G06F9/30083 ,  G06F1/3203 ,  G06F9/3013 ,  G06F9/30181 ,  G06F9/3836 ,  G06F9/3869 ,  G06F9/3885 ,  G06F11/302 ,  G06F11/3062 ,  G06F11/3096

    摘要： Mechanisms are provided for processing an instruction in a processor of a data processing system. The mechanisms operate to receive, in a processor of the data processing system, an instruction, the instruction including power/performance tradeoff information associated with the instruction. The mechanisms further operate to determine power/performance tradeoff priorities or criteria, specifying whether power conservation or performance is prioritized with regard to execution of the instruction, based on the power/performance tradeoff information. Moreover, the mechanisms process the instruction in accordance with the power/performance tradeoff priorities or criteria identified based on the power/performance tradeoff information of the instruction.

    摘要翻译： 提供了用于处理数据处理系统的处理器中的指令的机制。 这些机制操作以在数据处理系统的处理器中接收指令，该指令包括与指令相关联的功率/性能权衡信息。 这些机制进一步操作以基于功率/性能折衷信息来确定功率/性能折衷优先级或标准，指定功率节省或关于指令的执行是否优先的性能。 此外，机构根据功率/性能折衷优先级或基于指令的功率/性能折衷信息识别的标准处理指令。

    Mechanisms for Reducing DRAM Power Consumption
    9.
    发明申请
    Mechanisms for Reducing DRAM Power Consumption 失效
    降低DRAM功耗的机制

    公开(公告)号：US20110296097A1

    公开(公告)日：2011-12-01

    申请号：US12789019

    申请日：2010-05-27

    申请人： Elmootazbellah N. Elnozahy ,  Karthick Rajamani ,  William E. Speight ,  Lixin Zhang

    发明人： Elmootazbellah N. Elnozahy ,  Karthick Rajamani ,  William E. Speight ,  Lixin Zhang

    IPC分类号： G06F12/00

    CPC分类号： G06F1/3275 ,  G11C11/406 ,  G11C11/4094 ,  G11C2211/4065 ,  G11C2211/4067 ,  Y02D10/13 ,  Y02D10/14

    摘要： Mechanisms are provided for inhibiting precharging of memory cells of a dynamic random access memory (DRAM) structure. The mechanisms receive a command for accessing memory cells of the DRAM structure. The mechanisms further determine, based on the command, if precharging the memory cells following accessing the memory cells is to be inhibited. Moreover, the mechanisms send, in response to the determination indicating that precharging the memory cells is to be inhibited, a command to blocking logic of the DRAM structure to block precharging of the memory cells following accessing the memory cells.

    摘要翻译： 提供用于禁止动态随机存取存储器（DRAM）结构的存储器单元的预充电的机制。 这些机制接收到用于访问DRAM结构的存储单元的命令。 这些机制基于该命令进一步确定如果禁止在访问存储器单元之后对存储单元进行预充电。 此外，机构响应于指示要禁止对存储器单元进行预充电的确定，发送阻止DRAM结构的逻辑以阻止访问存储器单元之后的存储器单元的预充电的命令。