公开(公告)号：US09940418B2

公开(公告)日：2018-04-10

申请号：US14806566

申请日：2015-07-22

Applicant: Freescale Semiconductor, Inc.

Inventor： Srinivas Jallepalli ,  Jon S. Choy

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F17/5045 ,  G06F2217/10

Abstract: This disclosure describes a design tool that iteratively performs simulation sets on an integrated circuit design, each corresponding to a different hierarchical level with each of the simulation sets producing a different set of simulation results. Each of the simulation sets utilizes a different set of local parameter values that include extreme instance local parameter values based on the set of simulation results of a preceding simulation set. The design tool generates a set of hierarchically aggregated simulation results based upon the last set of simulation results and global parameters, and modifies the integrated circuit design based upon a yield estimation that is determined from comparing the set of hierarchically aggregated simulation results to specification requirements that correspond to the integrated circuit design.

公开(公告)号：US20170024502A1

公开(公告)日：2017-01-26

申请号：US14806566

申请日：2015-07-22

Applicant: Freescale Semiconductor, Inc.

Inventor： Srinivas Jallepalli ,  Jon S. Choy

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F17/5045 ,  G06F2217/10

Abstract: This disclosure describes a design tool that iteratively performs simulation sets on an integrated circuit design, each corresponding to a different hierarchical level with each of the simulation sets producing a different set of simulation results. Each of the simulation sets utilizes a different set of local parameter values that include extreme instance local parameter values based on the set of simulation results of a preceding simulation set. The design tool generates a set of hierarchically aggregated simulation results based upon the last set of simulation results and global parameters, and modifies the integrated circuit design based upon a yield estimation that is determined from comparing the set of hierarchically aggregated simulation results to specification requirements that correspond to the integrated circuit design.

Abstract translation: 本公开描述了一种设计工具，其迭代地执行集成电路设计上的模拟集合，每个模拟集合对应于不同的层级，每个模拟集合产生不同的模拟结果集合。 每个模拟集都使用不同的局部参数值集合，其包括基于先前模拟集合的模拟结果集的极端实例局部参数值。 设计工具基于最后一组仿真结果和全局参数生成一组分层聚合的仿真结果，并且基于通过将分层聚集的模拟结果集与规范要求进行比较而确定的产量估计来修改集成电路设计 对应于集成电路设计。