公开(公告)号：US09659622B1

公开(公告)日：2017-05-23

申请号：US15003922

申请日：2016-01-22

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Jon S. Choy

IPC: G11C11/00 ,  G11C11/16

CPC classification number: G11C11/1673 ,  G11C7/065 ,  G11C11/1659 ,  G11C11/1693 ,  G11C11/1695 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0061 ,  G11C27/024 ,  G11C2013/0054 ,  G11C2013/0057 ,  G11C2213/74 ,  G11C2213/79

Abstract: In a non-volatile memory, a method of performing a sensing operation to read a non-volatile (NV) element includes a first and a second phase. During the first phase, the NV element is coupled via a sense path transistor to a first capacitive element at a first input of an amplifier stage and a reference cell is coupled via a reference sense path transistor to a second capacitive element at a second input of the amplifier stage. During the second phase, the NV element is coupled via the sense path transistor to the second capacitive element and the reference cell is coupled via the reference sense path transistor to the first capacitive element. During the first phase, the first and second capacitive elements are initialized to voltages representative of states of the NV element and reference cell, respectively. During the second phase, the voltage differential between the two voltages is amplified.

公开(公告)号：US09621033B2

公开(公告)日：2017-04-11

申请号：US14849194

申请日：2015-09-09

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Jon S. Choy ,  Michael G. Neaves

IPC: H01L21/38 ,  H03K3/01 ,  H02M3/07 ,  H02M1/00

CPC classification number: H01L27/0222 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/092 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/78 ,  H02M3/07 ,  H02M2001/0041 ,  H02M2003/071 ,  H02M2003/077

Abstract: A charge pump comprises one or more pump stages for providing a negative boosted output voltage. Each of the one or more pump stages comprises a P-channel transistor formed in an isolated P-well and an N-channel transistor coupled in series with the P-channel transistor. Forming the P-channel transistor in the isolated P-well essentially eliminates a raised threshold voltage due to body effect.

公开(公告)号：US20140145765A1

公开(公告)日：2014-05-29

申请号：US13686889

申请日：2012-11-27

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Jon S. Choy ,  Richard Titov Lara Saez ,  Luis Eduardo Rueda Guerrero

IPC: H03L5/02

CPC classification number: H03L5/02 ,  G05F1/613

Abstract: Systems and methods for voltage ramp-up protection. In an illustrative, non-limiting embodiment, a method may include monitoring at least one of a first node or a second node, the first node configured to receive a first voltage greater than a second voltage present at a second node, and, in response to a slew rate of the first voltage creating a sneak condition between the first node and the second node, counteracting the sneak condition. For example, the sneak condition may favor an excess current to flow from the first node to the second node. In some cases, counteracting the sneak condition may include maintaining the second voltage below at or below a predetermined value.

Abstract translation: 电压提升保护的系统和方法。 在说明性的非限制性实施例中，方法可以包括监视第一节点或第二节点中的至少一个，第一节点被配置为接收大于第二节点处存在的第二电压的第一电压，并且作为响应 达到第一电压的转换速率，在第一节点和第二节点之间产生潜行状态，抵消潜行状态。 例如，潜行条件可能有利于从第一节点到第二节点的过量电流。 在一些情况下，抵消潜行状态可以包括将第二电压维持在等于或低于预定值。

公开(公告)号：US09940418B2

公开(公告)日：2018-04-10

申请号：US14806566

申请日：2015-07-22

Applicant: Freescale Semiconductor, Inc.

Inventor： Srinivas Jallepalli ,  Jon S. Choy

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F17/5045 ,  G06F2217/10

Abstract: This disclosure describes a design tool that iteratively performs simulation sets on an integrated circuit design, each corresponding to a different hierarchical level with each of the simulation sets producing a different set of simulation results. Each of the simulation sets utilizes a different set of local parameter values that include extreme instance local parameter values based on the set of simulation results of a preceding simulation set. The design tool generates a set of hierarchically aggregated simulation results based upon the last set of simulation results and global parameters, and modifies the integrated circuit design based upon a yield estimation that is determined from comparing the set of hierarchically aggregated simulation results to specification requirements that correspond to the integrated circuit design.

公开(公告)号：US20170024502A1

公开(公告)日：2017-01-26

申请号：US14806566

申请日：2015-07-22

Applicant: Freescale Semiconductor, Inc.

Inventor： Srinivas Jallepalli ,  Jon S. Choy

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F17/5045 ,  G06F2217/10

Abstract: This disclosure describes a design tool that iteratively performs simulation sets on an integrated circuit design, each corresponding to a different hierarchical level with each of the simulation sets producing a different set of simulation results. Each of the simulation sets utilizes a different set of local parameter values that include extreme instance local parameter values based on the set of simulation results of a preceding simulation set. The design tool generates a set of hierarchically aggregated simulation results based upon the last set of simulation results and global parameters, and modifies the integrated circuit design based upon a yield estimation that is determined from comparing the set of hierarchically aggregated simulation results to specification requirements that correspond to the integrated circuit design.

Abstract translation: 本公开描述了一种设计工具，其迭代地执行集成电路设计上的模拟集合，每个模拟集合对应于不同的层级，每个模拟集合产生不同的模拟结果集合。 每个模拟集都使用不同的局部参数值集合，其包括基于先前模拟集合的模拟结果集的极端实例局部参数值。 设计工具基于最后一组仿真结果和全局参数生成一组分层聚合的仿真结果，并且基于通过将分层聚集的模拟结果集与规范要求进行比较而确定的产量估计来修改集成电路设计 对应于集成电路设计。

公开(公告)号：US09484905B1

公开(公告)日：2016-11-01

申请号：US15003917

申请日：2016-01-22

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Khoi B. Mai ,  Jon S. Choy ,  Michael T. Berens

IPC: G11C27/02 ,  H03K5/00 ,  H03K17/00 ,  H03K17/06

CPC classification number: H03K17/08122 ,  G11C27/024 ,  H03K17/102

Abstract: A voltage switch for handling negative voltages includes an input terminal coupled to a voltage that is greater than a voltage rating of oxide in the voltage switch, a top capacitor plate pre-charge module including three cascoded p-channel transistors coupled between a supply voltage and a top plate of a capacitor, a bottom capacitor plate pre-charge module including two cascoded n-channel transistors coupled between a bottom plate of the capacitor and ground, and an output voltage module including an output terminal and four cascoded n-channel transistors with control electrodes of a first and fourth of the cascoded n-channel transistors coupled to a boost node. Control electrodes of a second and third of the cascoded n-channel transistors coupled to the top plate of the capacitor. A voltage switch for positive voltages is also disclosed.

Abstract translation: 用于处理负电压的电压开关包括耦合到大于电压开关中的氧化物的额定电压的电压的输入端子，顶部电容器板预充电模块，包括耦合在电源电压和电源电压之间的三个级联的p沟道晶体管 电容器的顶板，底部电容器板预充电模块，其包括耦合在电容器的底板和地之间的两个级联的n沟道晶体管，以及包括输出端子和四个级联的n沟道晶体管的输出电压模块，其具有 耦合到升压节点的级联的n沟道晶体管的第一和第四的控制电极。 耦合到电容器的顶板的第二和第三级联的n沟道晶体管的控制电极。 还公开了用于正电压的电压开关。

公开(公告)号：US08830776B1

公开(公告)日：2014-09-09

申请号：US13835068

申请日：2013-03-15

Applicant: Freescale Semiconductor, Inc.

Inventor： Jon S. Choy ,  Gilles J. Muller ,  Karthik Ramanan

IPC: G11C7/00 ,  G05F1/46

CPC classification number: G05F1/46 ,  H02M1/15 ,  H02M3/07 ,  H02M2001/0045 ,  H02M2003/071

Abstract: A negative charge pump is responsive to a pump enable signal. A voltage controlled current source provides a current. A resistor is coupled between a node from the voltage controlled current source and a negative charge output from the negative charge pump. A capacitor is placed in parallel with the resistor. A comparator generates the pump enable signal to control the negative charge pump. The comparator is coupled to the resistor and the capacitor and measures an IR drop thereacross and compares this measurement against a reference threshold. A level of the pump enable signal can be variable by tuning an amount of resistance of the resistor or capacitor or adjusting the reference threshold. A memory can be driven by a method of the negative charge pump.

Abstract translation: 负电荷泵响应于泵使能信号。 电压控制电流源提供电流。 电阻器耦合在来自压控电流源的节点和来自负电荷泵的负电荷输出之间。 电容器与电阻器并联放置。 比较器产生泵使能信号来控制负电荷泵。 比较器耦合到电阻器和电容器，并测量其上的IR电压，并将此测量值与参考阈值进行比较。 通过调节电阻或电容器的电阻量或调整参考阈值，可以使泵启用信号的电平可变。 存储器可以由负电荷泵的方法驱动。

公开(公告)号：US09640256B1

公开(公告)日：2017-05-02

申请号：US15165041

申请日：2016-05-26

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Anirban Roy ,  Jon S. Choy ,  Michael A. Sadd

IPC: G11C8/00 ,  G11C14/00 ,  H01L27/11 ,  H01L27/24 ,  G11C11/419 ,  G11C11/16

CPC classification number: G11C14/0081 ,  G11C11/005 ,  G11C11/1673 ,  G11C11/419 ,  G11C13/004 ,  G11C27/024 ,  G11C2013/0042 ,  G11C2013/0045 ,  H01L27/1104

Abstract: An integrated circuit (IC) device includes a static random access memory (SRAM) array, and a resistive memory (resistive memory) array. A first set of programmable resistive elements in the resistive memory array are used to store data from memory cells in the SRAM array. Sense amplifier circuitry is couplable to the SRAM array and the resistive memory array. An arbiter is configured to assert an resistive memory enable signal to couple the sense amplifier circuitry to the resistive memory array and decouple the sense amplifier circuitry from the SRAM array during a resistive memory read operation, and to couple the sense amplifier to the SRAM array and decouple the sense amplifier circuitry from the resistive memory array during an SRAM read operation.

公开(公告)号：US09449703B1

公开(公告)日：2016-09-20

申请号：US14734736

申请日：2015-06-09

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Anirban Roy ,  Jon S. Choy

IPC: G11C16/04 ,  G11C16/08 ,  G11C5/14 ,  G11C16/30

CPC classification number: G11C16/30 ,  G11C5/145 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/3418

Abstract: A nonvolatile memory includes a memory array having a plurality of memory cells, a select gate driver configured to provide a select gate voltage to a select gate of a first memory cell of the plurality of memory cells, and a control gate driver configured to use the select gate voltage to provide a control gate voltage to a control gate of a second memory cell of the plurality of memory cells.

Abstract translation: 非易失性存储器包括具有多个存储单元的存储器阵列，选择栅极驱动器，被配置为向多个存储单元中的第一存储单元的选择栅极提供选择栅极电压;以及控制栅极驱动器，其被配置为使用 选择栅极电压以向多个存储单元的第二存储单元的控制栅极提供控制栅极电压。