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公开(公告)号：US20100129781A1
公开(公告)日：2010-05-27
申请号：US12382151
申请日：2009-03-10
申请人： Fu-Cheng Wang , Hsiao-Wu Wang
发明人： Fu-Cheng Wang , Hsiao-Wu Wang
IPC分类号： G09B23/30
CPC分类号： G09B23/30
摘要： The invention discloses the electrical bronze acupuncture statue apparatus that comprises the electrical elements, the sensors and the embedded system. The invention simulates the acupuncture points for practicing the traditional Chinese medicine treatment and provides the virtual results.
摘要翻译： 本发明公开了一种电子元器件，传感器和嵌入式系统的青铜针灸雕刻装置。 本发明模拟了实践中药治疗的针灸穴位，并提供了虚拟成果。
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2.发明授权Structure and fabrication of field-effect transistor for alleviating short-channel effects 有权用于减轻短沟道效应的场效晶体管的结构和制造公开(公告)号：US07700980B1
公开(公告)日：2010-04-20
申请号：US11975278
申请日：2007-10-17
IPC分类号： H01L31/112
CPC分类号： H01L29/1083 , H01L21/823807 , H01L21/823814 , H01L29/105
摘要： Each of a pair of like-polarity IGFETs (40 or 42 and 240 or 242) has a channel zone (64 or 84) situated in body material (50). Short-channel effects are alleviated by arranging for the net dopant concentration in the channel zone to longitudinally reach a local surface minimum at a location between the IGFET's source/drain zones (60 and 62 or 80 and 82) and by arranging for the net dopant concentration in the body material to reach a local subsurface maximum more than 0.1 μm deep into the body material but not more than 0.4 μm deep into the body material. A pocket portion (100/102 or 104) extends along both source drain zones of one of the IGFETs. A pocket portion (244 or 246) extends largely along only one of the source/drain zones of the other IGFET so that it is an asymmetrical device.
摘要翻译： 一对相同极性的IGFET（40或42和240或242）中的每一个具有位于主体材料（50）中的通道区（64或84）。 通过设置沟道区域中的净掺杂剂浓度以在IGFET的源极/漏极区域（60和62或80和82）之间的位置处纵向达到局部表面最小值并且通过布置净掺杂剂来缓解短沟道效应 在身体材料中的浓度达到局部地下最大超过0.1μm深的身体材料，但不超过0.4μm深入身体材料。 袋部分（100/102或104）沿着IGFET之一的两个源极漏极区延伸。 袋部分（244或246）沿着另一个IGFET的源极/漏极区域中的一个较大地延伸，使得它是不对称的装置。
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公开(公告)号：US06461932B1
公开(公告)日：2002-10-08
申请号：US09211703
申请日：1998-12-14
申请人： Fu-Cheng Wang
发明人： Fu-Cheng Wang
IPC分类号： H01L21336
CPC分类号： H01L21/76229 , H01L21/31053
摘要： A trenched-isolated semiconductor structure is created by a process that entails forming a patterned trench (54) along an upper surface of a semiconductor body (40). A dielectric layer (56) is provided over the upper semiconductor surface. The dielectric layer is covered with a smoothening layer (60) whose upper surface is smoother than the upper surface of the dielectric layer. The smoothening layer is removed starting from its upper surface. During the removal of the smoothening layer, upward-protruding material of the dielectric layer progressively becomes exposed and is also removed. As a result, the remainder of dielectric layer has a smoother upper surface than the initial upper surface of the dielectric layer.
摘要翻译： 沟槽隔离半导体结构通过沿着半导体本体（40）的上表面形成图案化沟槽（54）的工艺产生。 介电层（56）设置在上半导体表面上。 电介质层被上表面比电介质层的上表面更平滑的平滑层（60）覆盖。 平滑层从其上表面开始去除。 在去除平滑层期间，电介质层的向上突出的材料逐渐变得暴露并且也被去除。 结果，电介质层的其余部分具有比介电层的初始上表面更平滑的上表面。
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公开(公告)号：US20120181620A1
公开(公告)日：2012-07-19
申请号：US12833844
申请日：2010-07-09
IPC分类号： H01L27/092
CPC分类号： H01L29/1083 , H01L21/823807 , H01L21/823814 , H01L29/105
摘要： An IGFET (40 or 42) has a channel zone (64 or 84) situated in body material (50). Short-channel threshold voltage roll-off and punchthrough are alleviated by arranging for the net dopant concentration in the channel zone to longitudinally reach a local surface minimum at a location between the IGFET's source/drain zones (60 and 62 or 80 and 82) and by arranging for the net dopant concentration in the body material to reach a local subsurface maximum more than 0.1 μm deep into the body material but not more than 0.1 μm deep into the body material. The source/drain zones (140 and 142 or 160 and 162) of a p-channel IGFET (120 or 122) are provided with graded-junction characteristics to reduce junction capacitance, thereby increasing switching speed.
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5.发明授权Fabrication of field-effect transistor with reduced junction capacitance and threshold voltage of magnitude that decreases with increasing channel length 有权具有减小的结电容和阈值电压的场效应晶体管的制造随着沟道长度的增加而减小公开(公告)号：US07879669B1
公开(公告)日：2011-02-01
申请号：US11527265
申请日：2006-09-25
IPC分类号： H01L29/78
CPC分类号： H01L29/1083 , H01L21/823807 , H01L21/823814 , H01L29/105
摘要： At least one source/drain zone (140, 142, 160, or 162) of an enhancement-mode insulated-gate field-effect transistor (120 or 122) is provided with graded junction characteristics to reduce junction capacitance, thereby increasing switching speed. Each graded junction source/drain zone contains a main portion (140M, 142M, 160M, or 162M) and a more lightly doped lower portion (140L, 142L, 160L, or 162L) underlying, and vertically continuous with, the main portion. The magnitudes of the threshold voltages of a group of such transistors fabricated under the same post-layout fabrication process conditions so as to be of different channel lengths reach a maximum absolute value VTAM when the channel length is at a value LC, are at least 0.03 volt less than VTAM when the channel length is approximately 0.3 μm greater than LC, and materially decrease with increasing channel length when the channel length is approximately 1.0 μm greater than LC.
摘要翻译： 提供增强型绝缘栅场效应晶体管（120或122）的至少一个源极/漏极区（140,142,160或162）具有渐变结特征以减小结电容，从而提高开关速度。 每个分级接点源极/漏极区域包含主要部分（140M，142M，160M或162M）和在主要部分下面并垂直连续的较轻掺杂的下部分（140L，142L，160L或162L）。 在通道长度为LC时，在相同布局前制造工艺条件下制造的一组这样的晶体管的阈值电压的幅度达到最大绝对值VTAM至少为0.03 当沟道长度比LC大约0.3μm时，小于VTAM的伏特，并且当沟道长度大于LC时大约1.0μm时，随着沟道长度的增加而实质上减小。
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6.发明申请公开(公告)号：US20100302100A1
公开(公告)日：2010-12-02
申请号：US12719294
申请日：2010-03-08
申请人： CHAO-TUNG YANG , Fu-Cheng Wang , Shoufang Chen , Shuo-Yuan Hsiao
发明人： CHAO-TUNG YANG , Fu-Cheng Wang , Shoufang Chen , Shuo-Yuan Hsiao
摘要： A signal processing apparatus for a multi-mode satellite positioning system includes a band-pass filter, a local oscillator circuit, a first mixing circuit, a second mixing circuit, an analog-to-digital converter and a baseband circuit. By properly allocating a local frequency, radio frequency (RF) signals of a Global Positioning System (GPS), a Galileo positioning system and a Global Navigation System (GLONASS) are processed via a single signal path to save hardware cost.
摘要翻译： 一种用于多模式卫星定位系统的信号处理装置，包括带通滤波器，本地振荡器电路，第一混频电路，第二混频电路，模数转换器和基带电路。 通过适当地分配本地频率，通过单个信号路径处理全球定位系统（GPS），伽利略定位系统和全球导航系统（GLONASS）的射频（RF）信号以节省硬件成本。
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7.发明授权Semiconductor structure in which like-polarity insulated-gate field-effect transistors have multiple vertical body dopant concentration maxima and different halo pocket characteristics 有权其中类似极性绝缘栅场效应晶体管具有多个垂直体掺杂浓度最大值和不同晕圈特征的半导体结构公开(公告)号：US07701005B1
公开(公告)日：2010-04-20
申请号：US11974751
申请日：2007-10-15
IPC分类号： H01L29/80
CPC分类号： H01L29/1083 , H01L21/823807 , H01L21/823814 , H01L29/105
摘要： Each of a pair of differently configured like-polarity insulated-gate field-effect transistors (40 or 42 and 240 or 242) in a semiconductor structure has a channel zone of semiconductor body material, a gate dielectric layer overlying the channel zone, and a gate electrode overlying the gate dielectric layer. For each transistor, the net dopant concentration of the body material reaches multiple local subsurface maxima below a channel surface depletion region and below largely all gate-electrode material overlying the channel zone. The transistors have source/drain zones (60 or 80) of opposite conductivity type to, and halo pocket portions of the same conductivity type as, the body material. One pocket portion (100/102 or 104) extends along both source/drain zones of one of the transistors. Another pocket portion (244 or 246) extends largely along only one of the source/drain zones of the other transistor so that it is asymmetrical.
摘要翻译： 半导体结构中的一对不同构造的相同极性的绝缘栅场效应晶体管（40或42和240或242）中的每一个具有半导体主体材料的沟道区，覆盖沟道区的栅介质层和 覆盖栅介电层的栅电极。 对于每个晶体管，主体材料的净掺杂剂浓度在沟道表面耗尽区下方达到多个局部地下极大值，并且大部分覆盖在沟道区上方的所有栅电极材料。 晶体管具有与主体材料相同的导电类型的源极/漏极区域（60或80）以及与主体材料相同的导电类型的卤素口袋部分。 一个口袋部分（100/102或104）沿着一个晶体管的源极/漏极区域延伸。 另一个口袋部分（244或246）沿着另一个晶体管的源极/漏极区域中的一个较大地延伸，使得它是不对称的。
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公开(公告)号：US08188683B2
公开(公告)日：2012-05-29
申请号：US12805658
申请日：2010-08-12
申请人： Bin-Juine Huang , Chun-Wen Tang , Fu-Cheng Wang
发明人： Bin-Juine Huang , Chun-Wen Tang , Fu-Cheng Wang
IPC分类号： G05F1/00
CPC分类号： H05B33/086 , H05B33/0866 , H05B33/0872
摘要： The invention discloses a novel control system for a Poly-Chromatic light-emitting diode (LED) lighting system, and applies feed forward and feedback control techniques to regulate the color and luminous outputs. Also, the control system is proposed for achieving luminous and color consistency for Poly-Chromatic LED lighting.
摘要翻译： 本发明公开了一种用于多色发光二极管（LED）照明系统的新型控制系统，并且使用前馈和反馈控制技术来调节颜色和发光输出。 此外，为了实现多色LED照明的发光和颜色一致性，提出了控制系统。
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9.发明申请公开(公告)号：US20110133049A1
公开(公告)日：2011-06-09
申请号：US12801520
申请日：2010-06-14
申请人： Fu-Cheng Wang , Min-Feng Hong
发明人： Fu-Cheng Wang , Min-Feng Hong
CPC分类号： G05D19/02 , F16F15/002
摘要： This invention discloses an optical table and the vibration control method thereof. Using disturbance response decomposing techniques, a double-layer structure is applied to independently control the ground and load disturbances. This invention can simplify the vibration control and improve system performance.
摘要翻译： 本发明公开了一种光学台及其振动控制方法。 使用扰动响应分解技术，应用双层结构来独立控制地面和负载扰动。 本发明可以简化振动控制，提高系统性能。
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10.发明授权公开(公告)号：US06599804B2
公开(公告)日：2003-07-29
申请号：US09947012
申请日：2001-09-04
IPC分类号： H01L21336
CPC分类号： H01L29/66492 , H01L21/26586 , H01L21/823807 , H01L21/823892 , H01L29/1045 , H01L29/105 , H01L29/665
摘要： Short-channel threshold voltage roll-off and punchthrough in an IGFET (40 or 42) having a channel zone (64 or 84) situated in body material (50) are alleviated by arranging for the net dopant concentration in the channel zone to longitudinally reach a local surface minimum at a location between the IGFET's source/drain zones (60 and 62 or 80 and 82) and by arranging for the net dopant concentration in the body material to reach a local subsurface maximum more than 0.1 &mgr;m deep into the body material but not more than 0.4 &mgr;m deep into the body material.
摘要翻译： 通过设置通道区域中的净掺杂剂浓度以纵向到达，减轻了具有位于主体材料（50）中的通道区（64或84）的IGFET（40或42）中的短通道阈值电压滚降和穿通 在IGFET源极/漏极区（60和62或80和82）之间的位置处的局部表面最小值，并且通过布置主体材料中的净掺杂剂浓度达到超过0.1μm深的主体材料的局部地下最大值 但不超过0.4 mum深入身材。
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