公开(公告)号：US20070169054A1

公开(公告)日：2007-07-19

申请号：US11471485

申请日：2006-06-21

申请人： Fu-Chiung Cheng ,  Kuan-Yu Yan ,  Jian-Yi Chen ,  Shu-Ming Chang ,  Ping-Yun Wang ,  Li-Kai Chang ,  Chin-Tai Chou ,  Ming-Shiou Chiang

发明人： Fu-Chiung Cheng ,  Kuan-Yu Yan ,  Jian-Yi Chen ,  Shu-Ming Chang ,  Ping-Yun Wang ,  Li-Kai Chang ,  Chin-Tai Chou ,  Ming-Shiou Chiang

IPC分类号： G06F9/45

CPC分类号： G06F8/74

摘要： A process of automatically translating a high level programming language into an extended activity diagram (EAD), which can translate source codes coded by the high level programming language into a corresponding activity diagram (AD) before the high level language is translated into a hardware description language (HDL). The process adds a new translation rule in a compiler and modifies the AD specification of a unified modeling language (UML) to accordingly translate the source codes into the AD and present the programming logic and executing flow of the source codes in a visualization form. In addition, the process can translate the high level programming language into a unified format for representation, and the AD can benefit simulation and requirement in a following HDL translation.

摘要翻译： 将高级编程语言自动翻译成扩展活动图（EAD）的过程，其可以在将高级语言转换为硬件描述之前将由高级编程语言编码的源代码转换为相应的活动图（AD） 语言（HDL）。 该过程在编译器中添加了一个新的翻译规则，并修改了统一建模语言（UML）的AD规范，从而将源代码转换为AD，并呈现编程逻辑，并以可视化形式执行源代码的流程。 此外，该过程可以将高级编程语言转换为统一的表示格式，AD可以在以下HDL翻译中受益于仿真和要求。

公开(公告)号：US20070157132A1

公开(公告)日：2007-07-05

申请号：US11472365

申请日：2006-06-22

申请人： Fu-Chiung Cheng ,  Jian-Yi Chen ,  Kuan-Yu Yan ,  Shin-Hway Yu ,  Kuan-Yu Chen ,  Chieh-Ju Wang ,  Shu-Ming Chang ,  Ping-Yun Wang ,  Li-Kai Chang ,  Chin-Tai Chou ,  Chi-Huam Shieh ,  Ming-Shiou Chiang ,  Nian-Zhi Huang ,  Hung-Chi Wu

发明人： Fu-Chiung Cheng ,  Jian-Yi Chen ,  Kuan-Yu Yan ,  Shin-Hway Yu ,  Kuan-Yu Chen ,  Chieh-Ju Wang ,  Shu-Ming Chang ,  Ping-Yun Wang ,  Li-Kai Chang ,  Chin-Tai Chou ,  Chi-Huam Shieh ,  Ming-Shiou Chiang ,  Nian-Zhi Huang ,  Hung-Chi Wu

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5045

摘要： A process of automatically translating a high level programming language into a hardware description language (HDL), which can use a three-stage translation mechanism to generate the HDL codes corresponding to the functions described by the high level programming language. The first stage translates source codes coded by the high level programming language into an extended activity diagram (EAD). The second stage translates the EAD into a hardware component graph (HCG). The third stage generates the respective signal connections of HDL components according to all edges of the HCG, and outputs an HDL entity and architecture to a file in a string form, thereby completing the entire translation.

摘要翻译： 自动将高级编程语言翻译成硬件描述语言（HDL）的过程，其可以使用三级转换机制来生成与由高级编程语言描述的功能相对应的HDL代码。 第一阶段将由高级编程语言编码的源代码转换为扩展活动图（EAD）。 第二阶段将EAD转换为硬件组件图（HCG）。 第三阶段根据HCG的所有边缘生成HDL组件的相应信号连接，并将HDL实体和体系结构输出到字符串形式的文件，从而完成整个翻译。

公开(公告)号：US07430727B2

公开(公告)日：2008-09-30

申请号：US11440065

申请日：2006-05-25

申请人： Fu-Chiung Cheng ,  Shu-Ming Chang ,  Jian-Yi Chen ,  Chieh-Ju Wang ,  Chin-Tai Chou ,  Nian-Zhi Huang ,  Chi-Huam Shieh ,  Ping-Yun Wang ,  Li-Kai Chang

发明人： Fu-Chiung Cheng ,  Shu-Ming Chang ,  Jian-Yi Chen ,  Chieh-Ju Wang ,  Chin-Tai Chou ,  Nian-Zhi Huang ,  Chi-Huam Shieh ,  Ping-Yun Wang ,  Li-Kai Chang

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： An HCG to HDL translation method, which can automatically generate VHDL codes. The method reads a hardware component graph (HCG) to find a start node and obtain a corresponding hardware component subgraph of the start node, analyzes all information of the start node to thereby add input and output components and generate a VHDL entity, determines types on all nodes of the hardware component, graph to thereby generate corresponding VHDL components and write associated information in a VHDL architecture, generates corresponding signal connections of VHDL components in accordance with edges of the hardware component graph, and outputs the VHDL entity and architecture to a file in a text form.

摘要翻译： 一种HCG到HDL的翻译方法，可以自动生成VHDL代码。 该方法读取硬件组件图（HCG）以找到起始节点并获取起始节点的相应硬件组件子图，分析起始节点的所有信息，从而添加输入和输出组件并生成VHDL实体，确定类型 硬件组件的所有节点图形，从而生成对应的VHDL组件并在VHDL架构中写入关联信息，根据硬件组件图的边缘生成VHDL组件的相应信号连接，并将VHDL实体和体系结构输出到文件 以文本形式。

公开(公告)号：US20070157147A1

公开(公告)日：2007-07-05

申请号：US11440065

申请日：2006-05-25

申请人： Fu-Chiung Cheng ,  Shu-Ming Chang ,  Jian-Yi Chen ,  Chieh-Ju Wang ,  Chin-Tai Chou ,  Nian-Zhi Huang ,  Chi-Huam Shieh ,  Ping-Yun Wang ,  Li-Kai Chang

发明人： Fu-Chiung Cheng ,  Shu-Ming Chang ,  Jian-Yi Chen ,  Chieh-Ju Wang ,  Chin-Tai Chou ,  Nian-Zhi Huang ,  Chi-Huam Shieh ,  Ping-Yun Wang ,  Li-Kai Chang

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： An HCG to HDL translation method, which can automatically generate VHDL codes. The method reads a hardware component graph (HCG) to find a start node and obtain a corresponding hardware component subgraph of the start node, analyzes all information of the start node to thereby add input and output components and generate a VHDL entity, determines types on all nodes of the hardware component, graph to thereby generate corresponding VHDL components and write associated information in a VHDL architecture, generates corresponding signal connections of VHDL components in accordance with edges of the hardware component graph, and outputs the VHDL entity and architecture to a file in a text form.

摘要翻译： 一种HCG到HDL的翻译方法，可以自动生成VHDL代码。 该方法读取硬件组件图（HCG）以找到起始节点并获取起始节点的相应硬件组件子图，分析起始节点的所有信息，从而添加输入和输出组件并生成VHDL实体，确定类型 硬件组件的所有节点图形，从而生成对应的VHDL组件并在VHDL架构中写入关联信息，根据硬件组件图的边缘生成VHDL组件的相应信号连接，并将VHDL实体和体系结构输出到文件 以文本形式。

公开(公告)号：US20070157187A1

公开(公告)日：2007-07-05

申请号：US11471483

申请日：2006-06-21

申请人： Fu-Chiung Cheng ,  Shin-Hway Yu ,  Kuan-Yu Chen ,  Jian-Yi Chen ,  Ming-Shiou Chiang ,  Shu-Ming Chang ,  Hung-Chi Wu ,  Ping-Yun Wang

发明人： Fu-Chiung Cheng ,  Shin-Hway Yu ,  Kuan-Yu Chen ,  Jian-Yi Chen ,  Ming-Shiou Chiang ,  Shu-Ming Chang ,  Hung-Chi Wu ,  Ping-Yun Wang

IPC分类号： G06F9/45 ,  G06F9/44

CPC分类号： G06F8/10 ,  G06F17/5045

摘要： A process of automatically translating an extended activity diagram (EAD) into a hardware component graph (HCG). For translating the high level programming language into a Very High Speed Integrated Circuit Hardware Description Language (VHDL), the high level programming language is first translated into an activity diagram (AD), then the AD is translated into an HCG, which can indicate a connection relation between hardware components, and finally corresponding HDL codes are generated according to the HCG

摘要翻译： 将扩展活动图（EAD）自动翻译成硬件组件图（HCG）的过程。 为了将高级编程语言转换为超高速集成电路硬件描述语言（VHDL），首先将高级编程语言转换为活动图（AD），然后将AD转换为HCG，其可以指示 硬件组件之间的连接关系，最后根据HCG生成相应的HDL代码

公开(公告)号：US20070157186A1

公开(公告)日：2007-07-05

申请号：US11407940

申请日：2006-04-21

申请人： Fu-Chiung Cheng ,  Shu-Ming Chang ,  Jian-Yi Chen ,  Kuan-Yu Yan ,  Shin-Hway Yu ,  Chin-Tai Chou

发明人： Fu-Chiung Cheng ,  Shu-Ming Chang ,  Jian-Yi Chen ,  Kuan-Yu Yan ,  Shin-Hway Yu ,  Chin-Tai Chou

IPC分类号： G06F9/45 ,  G06F9/44

CPC分类号： G06F17/5045

摘要： A method to hardware component graph translation process for a high-level programming language, which analyzes codes of a high-level programming language to collect class information and store the collected class information in a class information object, and generates a temporal hardware component graph to obtain corresponding public methods, parameters, return values. The public methods, parameters, return values are linked to a class start node. A method call table is generated according to both one or more in/out edges of a method call node and method information of the class information object. The one or more edges linked to the method call node are changed to a method start node according to the method call table to accordingly represent a respective method call in the codes of the high-level programming language and translate the temporal hardware component graph into a hardware component graph allowable to correspond to hardware components.

摘要翻译： 一种用于高级编程语言的硬件组件图形转换过程的方法，其分析高级编程语言的代码以收集类信息并将收集的类信息存储在类信息对象中，并且生成时间硬件组件图 获取相应的公共方法，参数，返回值。 公共方法，参数，返回值链接到类起始节点。 根据方法调用节点的一个或多个进/出边和类信息对象的方法信息生成方法调用表。 链接到方法调用节点的一个或多个边缘根据方法调用表被改变为方法开始节点，以相应地表示高级编程语言的代码中的相应方法调用，并将时间硬件组件图形转换为 硬件组件图可以对应于硬件组件。

公开(公告)号：US20070157134A1

公开(公告)日：2007-07-05

申请号：US11407955

申请日：2006-04-21

申请人： Fu-Chiung Cheng ,  Nian-Zhi Huang ,  Jian-Yi Chen

发明人： Fu-Chiung Cheng ,  Nian-Zhi Huang ,  Jian-Yi Chen

IPC分类号： G06F17/50

CPC分类号： G06F17/5022 ,  G01R31/318364

摘要： A method for testing a hardware circuit block written in a hardware description language (HDL) is provided, which can automatically produce a test pattern and an error message. The method includes converting an original class into a wrapper class, wherein the wrapper class, as compared to the original class, additionally records all input and output data of the hardware circuit block; producing a top module required for a hardware logic simulation; converting an original unit testing into an extended unit testing; using the extended unit testing to perform a unit testing on the wrapper class to thereby produce an input pattern file; and performing the hardware logic simulation on the hardware circuit block in accordance with the top module and the input pattern file.

摘要翻译： 提供了一种用于测试以硬件描述语言（HDL）编写的硬件电路块的方法，其可以自动产生测试模式和错误消息。 该方法包括将原始类转换为包装类，其中与初始类相比，包装类另外记录硬件电路块的所有输入和输出数据; 生成硬件逻辑仿真所需的顶级模块; 将原始单元测试转换为扩展单元测试; 使用扩展单元测试对包装类执行单元测试，从而产生输入模式文件; 并根据顶部模块和输入模式文件在硬件电路块上执行硬件逻辑仿真。

公开(公告)号：US07398507B2

公开(公告)日：2008-07-08

申请号：US11430987

申请日：2006-05-10

申请人： Li-Kai Chang ,  Fu-Chiung Cheng

发明人： Li-Kai Chang ,  Fu-Chiung Cheng

IPC分类号： G06F17/50

CPC分类号： B82Y10/00 ,  G06N99/002

摘要： A method of automatic synthesis of sequential quantum Boolean circuits for transferring a self-timed circuit into a sequential quantum Boolean circuit and synthesizing the sequential quantum Boolean circuit, which comprises the steps of: (A) transferring the self-timed circuit into a state graph having M state nodes, where M is an integer; (B) determining whether the state graph is reversible; (C) encoding the M state nodes by using a unique state encoding when step (B) decides that the state graph is reversible, and producing a unique state coding reversible state graph; (D) transferring the unique state coding reversible state graph (USCRSG) into a corresponding self-timed transformation graph; (E) performing a state decomposition on the self-timed transformation graph and producing a decomposed self-timed transformation graph; and (F) constructing a quantum Boolean circuit of the decomposed self-timed transformation graph.

摘要翻译： 一种自动合成顺序量子布尔电路的方法，用于将自定时电路传送到顺序量子布尔电路中，并合成顺序量子布尔电路，其包括以下步骤：（A）将自定时电路传送到状态图 具有M个状态节点，其中M是整数; （B）确定状态图是否可逆; （C）当步骤（B）判定状态图是可逆的时，通过使用唯一状态编码对M个状态节点进行编码，并产生唯一的状态编码可逆状态图; （D）将唯一状态编码可逆状态图（USCRSG）转移到相应的自定时变换图中; （E）对自适应变换图进行状态分解并产生分解的自时变换图; 和（F）构建分解的自定时变换图的量子布尔电路。

公开(公告)号：US20070266347A1

公开(公告)日：2007-11-15

申请号：US11430987

申请日：2006-05-10

申请人： Li-Kai Chang ,  Fu-Chiung Cheng

发明人： Li-Kai Chang ,  Fu-Chiung Cheng

IPC分类号： G06F17/50

CPC分类号： B82Y10/00 ,  G06N99/002

摘要： A method of automatic synthesis of sequential quantum Boolean circuits for transferring a self-timed circuit into a sequential quantum Boolean circuit and synthesizing the sequential quantum Boolean circuit, which comprises the steps of: (A) transferring the self-timed circuit into a state graph having M state nodes, where M is an integer; (B) determining whether the state graph is reversible; (C) encoding the M state nodes by using a unique state encoding when step (B) decides that the state graph is reversible, and producing a unique state coding reversible state graph; (D) transferring the unique state coding reversible state graph (USCRSG) into a corresponding self-timed transformation graph; (E) performing a state decomposition on the self-timed transformation graph and producing a decomposed self-timed transformation graph; and (F) constructing a quantum Boolean circuit of the decomposed self-timed transformation graph.

摘要翻译： 一种自动合成顺序量子布尔电路的方法，用于将自定时电路传送到顺序量子布尔电路中，并合成顺序量子布尔电路，其包括以下步骤：（A）将自定时电路传送到状态图 具有M个状态节点，其中M是整数; （B）确定状态图是否可逆; （C）当步骤（B）判定状态图是可逆的时，通过使用唯一状态编码对M个状态节点进行编码，并产生唯一的状态编码可逆状态图; （D）将唯一状态编码可逆状态图（USCRSG）转移到相应的自定时变换图中; （E）对自适应变换图进行状态分解并产生分解的自时变换图; 和（F）构建分解的自定时变换图的量子布尔电路。

公开(公告)号：US07307450B2

公开(公告)日：2007-12-11

申请号：US11171217

申请日：2005-07-01

申请人： Fang-Jia Liang ,  Fu-Chiung Cheng

发明人： Fang-Jia Liang ,  Fu-Chiung Cheng

IPC分类号： G06F7/38

CPC分类号： H03K19/1774 ,  H03K19/1737 ,  H03K19/17728

摘要： A programmable logic block for an asynchronous circuit design is disclosed. After a programmable setup, the logic block not only has the processing function of common devices, but also communicates using the asynchronous protocol so as to design an asynchronous device.

摘要翻译： 公开了一种用于异步电路设计的可编程逻辑块。 在可编程设置之后，逻辑块不仅具有通用设备的处理功能，而且还使用异步协议进行通信，以设计异步设备。