公开(公告)号：US07685552B2

公开(公告)日：2010-03-23

申请号：US11690985

申请日：2007-03-26

申请人： Fujio Ishihara ,  Ryubi Okuda ,  Toshihiko Himeno ,  Hiroshige Fujii

发明人： Fujio Ishihara ,  Ryubi Okuda ,  Toshihiko Himeno ,  Hiroshige Fujii

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F2217/62 ,  G06F2217/84

摘要： This invention concerns a semiconductor integrated circuit device comprising a plurality of circuit elements arranged in a chip and operating in response to a same clock signal; clock buffers arranged at intersecting points decided based on positions of the plurality of circuit elements, the intersecting points being included in intersecting points of a pseudo mesh virtually assumed to cover up a region in the chip including the plurality of circuit elements; and a main wiring transmitting the clock signal to the clock buffers.

摘要翻译： 本发明涉及一种半导体集成电路器件，其包括布置在芯片中并响应于相同时钟信号而工作的多个电路元件; 布置在基于多个电路元件的位置确定的相交点处的时钟缓冲器，所述交点包括在虚拟网格的相交点中，虚拟地假定为覆盖包括多个电路元件的芯片中的区域; 以及将时钟信号发送到时钟缓冲器的主线。

公开(公告)号：US20070240087A1

公开(公告)日：2007-10-11

申请号：US11690985

申请日：2007-03-26

申请人： Fujio ISHIHARA ,  Ryubi Okuda ,  Toshihiko Himeno ,  Hiroshige Fujii

发明人： Fujio ISHIHARA ,  Ryubi Okuda ,  Toshihiko Himeno ,  Hiroshige Fujii

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5045 ,  G06F2217/62 ,  G06F2217/84

摘要： This invention concerns a semiconductor integrated circuit device comprising a plurality of circuit elements arranged in a chip and operating in response to a same clock signal; clock buffers arranged at intersecting points decided based on positions of the plurality of circuit elements, the intersecting points being included in intersecting points of a pseudo mesh virtually assumed to cover up a region in the chip including the plurality of circuit elements; and a main wiring transmitting the clock signal to the clock buffers.

摘要翻译： 本发明涉及一种半导体集成电路器件，其包括布置在芯片中并响应于相同时钟信号而工作的多个电路元件; 布置在基于多个电路元件的位置确定的相交点处的时钟缓冲器，所述交点包括在虚拟网格的相交点中，虚拟地假定为覆盖包括多个电路元件的芯片中的区域; 以及将时钟信号发送到时钟缓冲器的主线。

公开(公告)号：US20050218941A1

公开(公告)日：2005-10-06

申请号：US10965661

申请日：2004-10-15

申请人： Natsuki Kushiyama ,  Ryubi Okuda

发明人： Natsuki Kushiyama ,  Ryubi Okuda

IPC分类号： H03K17/13 ,  H03B1/00 ,  H03K17/041 ,  H03K17/687 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/0185 ,  H03K19/094 ,  H03K19/0948 ,  H04L25/02

CPC分类号： H03K19/018514 ,  H03K17/04106 ,  H03K19/018528

摘要： A driver circuit disclosed herein comprises a first inverter which comprises: a first transistor which is connected between a first power supply with a first voltage and a first output node; a second transistor which is connected between the first output node and a second power supply with a second voltage; and a voltage maintaining circuit which is provided between the second power supply and the second transistor and which maintains a voltage of the first output node in the vicinity of a threshold voltage of a transistor which is connected to the first output node even when the second transistor is turned on.

摘要翻译： 本文公开的驱动器电路包括第一反相器，其包括：连接在具有第一电压的第一电源和第一输出节点之间的第一晶体管; 第二晶体管，其连接在第一输出节点和具有第二电压的第二电源之间; 以及电压保持电路，其设置在所述第二电源和所述第二晶体管之间，并且即使当所述第二晶体管与所述第二晶体管连接时，所述第一输出节点的电压保持在连接到所述第一输出节点的晶体管的阈值电压附近 打开

公开(公告)号：US07113007B2

公开(公告)日：2006-09-26

申请号：US10965661

申请日：2004-10-15

申请人： Natsuki Kushiyama ,  Ryubi Okuda

发明人： Natsuki Kushiyama ,  Ryubi Okuda

IPC分类号： H03K3/00

CPC分类号： H03K19/018514 ,  H03K17/04106 ,  H03K19/018528

摘要： A driver circuit disclosed herein comprises a first inverter which comprises: a first transistor which is connected between a first power supply with a first voltage and a first output node; a second transistor which is connected between the first output node and a second power supply with a second voltage; and a voltage maintaining circuit which is provided between the second power supply and the second transistor and which maintains a voltage of the first output node in the vicinity of a threshold voltage of a transistor which is connected to the first output node even when the second transistor is turned on.

摘要翻译： 本文公开的驱动器电路包括第一反相器，其包括：连接在具有第一电压的第一电源和第一输出节点之间的第一晶体管; 第二晶体管，其连接在第一输出节点和具有第二电压的第二电源之间; 以及电压保持电路，其设置在所述第二电源和所述第二晶体管之间，并且即使当所述第二晶体管与所述第二晶体管连接时，所述第一输出节点的电压保持在连接到所述第一输出节点的晶体管的阈值电压附近 打开