公开(公告)号：US10658335B2

公开(公告)日：2020-05-19

申请号：US15880455

申请日：2018-01-25

Applicant: Futurewei Technologies, Inc.

Inventor： Shiqun Gu ,  Yu Lin ,  Jinghua Zhu ,  Guofang Jiao

IPC: H01L23/48 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L25/10 ,  H01L23/64

Abstract: An integrated circuit package and a system including the integrated circuit package as well as a process for assembling the integrated circuit package are provided. The integrated circuit package includes a first die manufactured on a first wafer utilizing a first node size, a second die manufactured on a second wafer utilizing a second node size, and a substrate coupled to the second die at a plurality of bump sites on a bottom surface of the second die. The first die may be mounted on a top surface of the second die utilizing a hybrid wafer bonding technique, micro bumps, or electrode-less plating.

公开(公告)号：US20180366442A1

公开(公告)日：2018-12-20

申请号：US15880455

申请日：2018-01-25

Applicant: Futurewei Technologies, Inc.

Inventor： Shiqun Gu ,  Yu Lin ,  Jinghua Zhu ,  Guofang Jiao

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00

Abstract: An integrated circuit package and a system including the integrated circuit package as well as a process for assembling the integrated circuit package are provided. The integrated circuit package includes a first die manufactured on a first wafer utilizing a first node size, a second die manufactured on a second wafer utilizing a second node size, and a substrate coupled to the second die at a plurality of bump sites on a bottom surface of the second die. The first die may be mounted on a top surface of the second die utilizing a hybrid wafer bonding technique, micro bumps, or electrode-less plating.